anv/pipeline: Populate keys up-front
Instead of having each anv_pipeline_compile_* function populate the shader key, make it part of the anv_pipeline_stage struct and fill it out up-front. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
Jason Ekstrand
parent
76503b319a
commit
4a8236ae17
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@ -398,13 +398,14 @@ struct anv_pipeline_stage {
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const struct anv_shader_module *module;
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const char *entrypoint;
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const VkSpecializationInfo *spec_info;
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union brw_any_prog_key key;
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};
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static void
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anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
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struct anv_pipeline_layout *layout,
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struct anv_pipeline_stage *stage,
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const void *key, size_t key_size,
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unsigned char *sha1_out)
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{
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struct mesa_sha1 ctx;
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@ -426,7 +427,7 @@ anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
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_mesa_sha1_update(&ctx, stage->spec_info->pData,
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stage->spec_info->dataSize);
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}
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_mesa_sha1_update(&ctx, key, key_size);
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_mesa_sha1_update(&ctx, &stage->key, brw_prog_key_size(stage->stage));
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_mesa_sha1_final(&ctx, sha1_out);
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}
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@ -527,16 +528,12 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
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{
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const struct brw_compiler *compiler =
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pipeline->device->instance->physicalDevice.compiler;
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struct brw_vs_prog_key key;
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struct anv_shader_bin *bin = NULL;
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populate_vs_prog_key(&pipeline->device->info, &key);
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ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
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unsigned char sha1[20];
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anv_pipeline_hash_shader(pipeline, layout, stage,
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&key, sizeof(key), sha1);
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anv_pipeline_hash_shader(pipeline, layout, stage, sha1);
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bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
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if (bin == NULL) {
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@ -566,8 +563,8 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
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nir->info.separate_shader);
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const unsigned *shader_code =
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brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
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-1, NULL);
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brw_compile_vs(compiler, NULL, mem_ctx, &stage->key.vs,
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&prog_data, nir, -1, NULL);
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if (shader_code == NULL) {
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ralloc_free(mem_ctx);
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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@ -642,24 +639,15 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
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const struct gen_device_info *devinfo = &pipeline->device->info;
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const struct brw_compiler *compiler =
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pipeline->device->instance->physicalDevice.compiler;
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struct brw_tcs_prog_key tcs_key = {};
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struct brw_tes_prog_key tes_key = {};
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struct anv_shader_bin *tcs_bin = NULL;
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struct anv_shader_bin *tes_bin = NULL;
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populate_tcs_prog_key(&pipeline->device->info,
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info->pTessellationState->patchControlPoints,
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&tcs_key);
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populate_tes_prog_key(&pipeline->device->info, &tes_key);
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ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
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unsigned char tcs_sha1[40];
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unsigned char tes_sha1[40];
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anv_pipeline_hash_shader(pipeline, layout, tcs_stage,
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&tcs_key, sizeof(tcs_key), tcs_sha1);
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anv_pipeline_hash_shader(pipeline, layout, tes_stage,
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&tes_key, sizeof(tes_key), tes_sha1);
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anv_pipeline_hash_shader(pipeline, layout, tcs_stage, tcs_sha1);
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anv_pipeline_hash_shader(pipeline, layout, tes_stage, tes_sha1);
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memcpy(&tcs_sha1[20], tes_sha1, 20);
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memcpy(&tes_sha1[20], tcs_sha1, 20);
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@ -711,23 +699,25 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
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* this comes from the SPIR-V, which is part of the hash used for the
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* pipeline cache. So it should be safe.
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*/
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tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
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tcs_key.outputs_written = tcs_nir->info.outputs_written;
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tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written;
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tcs_key.quads_workaround =
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tcs_stage->key.tcs.tes_primitive_mode = tes_nir->info.tess.primitive_mode;
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tcs_stage->key.tcs.outputs_written = tcs_nir->info.outputs_written;
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tcs_stage->key.tcs.patch_outputs_written =
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tcs_nir->info.patch_outputs_written;
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tcs_stage->key.tcs.quads_workaround =
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devinfo->gen < 9 &&
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tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
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tes_nir->info.tess.spacing == TESS_SPACING_EQUAL;
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tes_key.inputs_read = tcs_key.outputs_written;
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tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
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tes_stage->key.tes.inputs_read = tcs_nir->info.outputs_written;
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tes_stage->key.tes.patch_inputs_read =
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tcs_nir->info.patch_outputs_written;
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const int shader_time_index = -1;
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const unsigned *shader_code;
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shader_code =
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brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
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tcs_nir, shader_time_index, NULL);
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brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_stage->key.tcs,
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&tcs_prog_data, tcs_nir, shader_time_index, NULL);
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if (shader_code == NULL) {
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ralloc_free(mem_ctx);
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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@ -748,7 +738,7 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
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}
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shader_code =
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brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
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brw_compile_tes(compiler, NULL, mem_ctx, &tes_stage->key.tes,
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&tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
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NULL, shader_time_index, NULL);
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if (shader_code == NULL) {
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@ -787,16 +777,12 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
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{
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const struct brw_compiler *compiler =
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pipeline->device->instance->physicalDevice.compiler;
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struct brw_gs_prog_key key;
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struct anv_shader_bin *bin = NULL;
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populate_gs_prog_key(&pipeline->device->info, &key);
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ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
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unsigned char sha1[20];
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anv_pipeline_hash_shader(pipeline, layout, stage,
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&key, sizeof(key), sha1);
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anv_pipeline_hash_shader(pipeline, layout, stage, sha1);
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bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
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if (bin == NULL) {
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@ -826,8 +812,8 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
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nir->info.separate_shader);
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const unsigned *shader_code =
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brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
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NULL, -1, NULL);
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brw_compile_gs(compiler, NULL, mem_ctx, &stage->key.gs,
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&prog_data, nir, NULL, -1, NULL);
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if (shader_code == NULL) {
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ralloc_free(mem_ctx);
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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@ -862,24 +848,19 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
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{
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const struct brw_compiler *compiler =
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pipeline->device->instance->physicalDevice.compiler;
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struct brw_wm_prog_key key;
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struct anv_shader_bin *bin = NULL;
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populate_wm_prog_key(&pipeline->device->info, pipeline->subpass,
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info->pMultisampleState, &key);
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/* TODO: we could set this to 0 based on the information in nir_shader, but
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* we need this before we call spirv_to_nir.
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*/
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const struct brw_vue_map *vue_map =
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&anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
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key.input_slots_valid = vue_map->slots_valid;
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stage->key.wm.input_slots_valid = vue_map->slots_valid;
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ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
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unsigned char sha1[20];
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anv_pipeline_hash_shader(pipeline, layout, stage,
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&key, sizeof(key), sha1);
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anv_pipeline_hash_shader(pipeline, layout, stage, sha1);
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bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
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if (bin == NULL) {
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@ -917,7 +898,7 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
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const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
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/* Unused or out-of-bounds */
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if (rt >= MAX_RTS || !(key.color_outputs_valid & (1 << rt)))
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if (rt >= MAX_RTS || !(stage->key.wm.color_outputs_valid & (1 << rt)))
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continue;
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const unsigned array_len =
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@ -948,7 +929,8 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
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continue;
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const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
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if (rt >= MAX_RTS || !(key.color_outputs_valid & (1 << rt))) {
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if (rt >= MAX_RTS ||
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!(stage->key.wm.color_outputs_valid & (1 << rt))) {
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/* Unused or out-of-bounds, throw it away */
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deleted_output = true;
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var->data.mode = nir_var_local;
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@ -978,8 +960,8 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
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/* Now that we've determined the actual number of render targets, adjust
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* the key accordingly.
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*/
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key.nr_color_regions = num_rts;
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key.color_outputs_valid = (1 << num_rts) - 1;
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stage->key.wm.nr_color_regions = num_rts;
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stage->key.wm.color_outputs_valid = (1 << num_rts) - 1;
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assert(num_rts <= max_rt);
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map.surface_to_descriptor -= num_rts;
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@ -991,8 +973,8 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
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anv_fill_binding_table(&prog_data.base, num_rts);
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const unsigned *shader_code =
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brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
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NULL, -1, -1, -1, true, false, NULL, NULL);
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brw_compile_fs(compiler, NULL, mem_ctx, &stage->key.wm, &prog_data,
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nir, NULL, -1, -1, -1, true, false, NULL, NULL);
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if (shader_code == NULL) {
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ralloc_free(mem_ctx);
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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@ -1036,16 +1018,14 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
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.spec_info = spec_info,
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};
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struct brw_cs_prog_key key;
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struct anv_shader_bin *bin = NULL;
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populate_cs_prog_key(&pipeline->device->info, &key);
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populate_cs_prog_key(&pipeline->device->info, &stage.key.cs);
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ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
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unsigned char sha1[20];
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anv_pipeline_hash_shader(pipeline, layout, &stage,
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&key, sizeof(key), sha1);
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anv_pipeline_hash_shader(pipeline, layout, &stage, sha1);
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bin = anv_device_search_for_kernel(pipeline->device, cache, sha1, 20);
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if (bin == NULL) {
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@ -1072,8 +1052,8 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
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anv_fill_binding_table(&prog_data.base, 1);
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const unsigned *shader_code =
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brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
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-1, NULL);
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brw_compile_cs(compiler, NULL, mem_ctx, &stage.key.cs,
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&prog_data, nir, -1, NULL);
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if (shader_code == NULL) {
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ralloc_free(mem_ctx);
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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@ -1372,6 +1352,31 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
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stages[stage].module = anv_shader_module_from_handle(sinfo->module);
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stages[stage].entrypoint = sinfo->pName;
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stages[stage].spec_info = sinfo->pSpecializationInfo;
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const struct gen_device_info *devinfo = &device->info;
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switch (stage) {
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case MESA_SHADER_VERTEX:
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populate_vs_prog_key(devinfo, &stages[stage].key.vs);
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break;
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case MESA_SHADER_TESS_CTRL:
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populate_tcs_prog_key(devinfo,
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pCreateInfo->pTessellationState->patchControlPoints,
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&stages[stage].key.tcs);
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break;
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case MESA_SHADER_TESS_EVAL:
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populate_tes_prog_key(devinfo, &stages[stage].key.tes);
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break;
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case MESA_SHADER_GEOMETRY:
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populate_gs_prog_key(devinfo, &stages[stage].key.gs);
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break;
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case MESA_SHADER_FRAGMENT:
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populate_wm_prog_key(devinfo, pipeline->subpass,
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pCreateInfo->pMultisampleState,
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&stages[stage].key.wm);
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break;
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default:
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unreachable("Invalid graphics shader stage");
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}
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}
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if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
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