From 4a758a17da7dd7366b98cee9b6312bf350102ad1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 29 Jul 2017 01:14:09 +0200 Subject: [PATCH] winsys/amdgpu: enable computation of tile swizzle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Dave Airlie Reviewed-by: Nicolai Hähnle --- src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 12 +++++++++++- src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index d438b6d662b..99e4d778df2 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -92,7 +92,17 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, config.info.levels = tex->last_level + 1; config.is_3d = !!(tex->target == PIPE_TEXTURE_3D); config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE); - config.info.surf_index = NULL; + + /* Use different surface counters for color and FMASK, so that MSAA MRTs + * always use consecutive surface indices when FMASK is allocated between + * them. + */ + if (flags & RADEON_SURF_FMASK) + config.info.surf_index = &ws->surf_index_fmask; + else if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) + config.info.surf_index = &ws->surf_index_color; + else + config.info.surf_index = NULL; return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf); } diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h index 7cd2f204842..7aca612f452 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h @@ -57,6 +57,8 @@ struct amdgpu_winsys { int num_cs; /* The number of command streams created. */ unsigned num_total_rejected_cs; + uint32_t surf_index_color; + uint32_t surf_index_fmask; uint32_t next_bo_unique_id; uint64_t allocated_vram; uint64_t allocated_gtt;