intel: Add INTEL_DEBUG=noccs alias for INTEL_DEBUG=norbc

When CCS compression first came out on Skylake, we referred to it as
"renderbuffer compression", or RBC for short.  However, that name has
long since fallen out of favor, and we refer to it as CCS nearly
everywhere.

This patch renames DEBUG_NO_RBC to DEBUG_NO_CCS inside the codebase
for clarity, and adds INTEL_DEBUG=noccs.  The legacy INTEL_DEBUG=norbc
name continues to work, because it's one line of code and having both
names makes our lives easier in the interim.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15447>
This commit is contained in:
Kenneth Graunke 2022-03-18 01:31:39 -07:00 committed by Marge Bot
parent 85d30846db
commit 49dd707ca2
7 changed files with 12 additions and 11 deletions

View File

@ -287,8 +287,8 @@ Intel driver environment variables
suppress generation of dual-object geometry shader code
``nofc``
disable fast clears
``norbc``
disable single sampled render buffer compression
``noccs``
disable lossless color compression
``optimizer``
dump shader assembly to files at each optimization pass and
iteration that make progress

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@ -447,7 +447,7 @@ crocus_resource_configure_aux(struct crocus_screen *screen,
isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
const bool has_ccs =
((devinfo->ver >= 7 && !res->mod_info && !INTEL_DEBUG(DEBUG_NO_RBC)) ||
((devinfo->ver >= 7 && !res->mod_info && !INTEL_DEBUG(DEBUG_NO_CCS)) ||
(res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) &&
isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, NULL,
&res->aux.surf, 0);

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@ -108,7 +108,7 @@ modifier_is_supported(const struct intel_device_info *devinfo,
/* Check remaining requirements. */
switch (modifier) {
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (INTEL_DEBUG(DEBUG_NO_RBC))
if (INTEL_DEBUG(DEBUG_NO_CCS))
return false;
if (pfmt != PIPE_FORMAT_BGRA8888_UNORM &&
@ -127,7 +127,7 @@ modifier_is_supported(const struct intel_device_info *devinfo,
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_CCS: {
if (INTEL_DEBUG(DEBUG_NO_RBC))
if (INTEL_DEBUG(DEBUG_NO_CCS))
return false;
enum isl_format rt_format =
@ -756,7 +756,7 @@ iris_resource_configure_aux(struct iris_screen *screen,
const bool has_hiz = !INTEL_DEBUG(DEBUG_NO_HIZ) &&
isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
const bool has_ccs = !INTEL_DEBUG(DEBUG_NO_RBC) &&
const bool has_ccs = !INTEL_DEBUG(DEBUG_NO_CCS) &&
iris_get_ccs_surf_or_support(&screen->isl_dev, &res->surf,
&res->aux.surf, &res->aux.extra_aux.surf);

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@ -76,7 +76,8 @@ static const struct debug_control debug_control[] = {
{ "tes", DEBUG_TES },
{ "l3", DEBUG_L3 },
{ "do32", DEBUG_DO32 },
{ "norbc", DEBUG_NO_RBC },
{ "norbc", DEBUG_NO_CCS },
{ "noccs", DEBUG_NO_CCS },
{ "nohiz", DEBUG_NO_HIZ },
{ "color", DEBUG_COLOR },
{ "reemit", DEBUG_REEMIT },

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@ -76,7 +76,7 @@ extern uint64_t intel_debug;
#define DEBUG_TES (1ull << 28)
#define DEBUG_L3 (1ull << 29)
#define DEBUG_DO32 (1ull << 30)
#define DEBUG_NO_RBC (1ull << 31)
#define DEBUG_NO_CCS (1ull << 31)
#define DEBUG_NO_HIZ (1ull << 32)
#define DEBUG_COLOR (1ull << 33)
#define DEBUG_REEMIT (1ull << 34)

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@ -160,7 +160,7 @@ isl_drm_modifier_get_score(const struct intel_device_info *devinfo,
if (devinfo->ver >= 12)
return 0;
if (INTEL_DEBUG(DEBUG_NO_RBC))
if (INTEL_DEBUG(DEBUG_NO_CCS))
return 0;
return 4;

View File

@ -657,7 +657,7 @@ add_aux_surface_if_supported(struct anv_device *device,
return add_aux_state_tracking_buffer(device, image, plane);
} else if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
if (INTEL_DEBUG(DEBUG_NO_RBC))
if (INTEL_DEBUG(DEBUG_NO_CCS))
return VK_SUCCESS;
if (!isl_surf_supports_ccs(&device->isl_dev,
@ -687,7 +687,7 @@ add_aux_surface_if_supported(struct anv_device *device,
return VK_SUCCESS;
}
if (INTEL_DEBUG(DEBUG_NO_RBC))
if (INTEL_DEBUG(DEBUG_NO_CCS))
return VK_SUCCESS;
ok = isl_surf_get_ccs_surf(&device->isl_dev,