diff --git a/src/intel/vulkan/anv_descriptor_set.c b/src/intel/vulkan/anv_descriptor_set.c index a31cc84bb52..964180c5f96 100644 --- a/src/intel/vulkan/anv_descriptor_set.c +++ b/src/intel/vulkan/anv_descriptor_set.c @@ -35,6 +35,53 @@ * Descriptor set layouts. */ +static enum anv_descriptor_data +anv_descriptor_data_for_type(const struct anv_physical_device *device, + VkDescriptorType type) +{ + enum anv_descriptor_data data = 0; + + switch (type) { + case VK_DESCRIPTOR_TYPE_SAMPLER: + data = ANV_DESCRIPTOR_SAMPLER_STATE; + break; + + case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: + data = ANV_DESCRIPTOR_SURFACE_STATE | + ANV_DESCRIPTOR_SAMPLER_STATE; + break; + + case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: + case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: + case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: + data = ANV_DESCRIPTOR_SURFACE_STATE; + break; + + case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: + case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: + data = ANV_DESCRIPTOR_SURFACE_STATE; + if (device->info.gen < 9) + data |= ANV_DESCRIPTOR_IMAGE_PARAM; + break; + + case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: + case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: + data = ANV_DESCRIPTOR_SURFACE_STATE | + ANV_DESCRIPTOR_BUFFER_VIEW; + break; + + case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: + case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: + data = ANV_DESCRIPTOR_SURFACE_STATE; + break; + + default: + unreachable("Unsupported descriptor type"); + } + + return data; +} + void anv_GetDescriptorSetLayoutSupport( VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, @@ -141,6 +188,7 @@ VkResult anv_CreateDescriptorSetLayout( /* Initialize all binding_layout entries to -1 */ memset(&set_layout->binding[b], -1, sizeof(set_layout->binding[b])); + set_layout->binding[b].data = 0; set_layout->binding[b].array_size = 0; set_layout->binding[b].immutable_samplers = NULL; } @@ -148,9 +196,6 @@ VkResult anv_CreateDescriptorSetLayout( /* Initialize all samplers to 0 */ memset(samplers, 0, immutable_sampler_count * sizeof(*samplers)); - uint32_t sampler_count[MESA_SHADER_STAGES] = { 0, }; - uint32_t surface_count[MESA_SHADER_STAGES] = { 0, }; - uint32_t image_param_count[MESA_SHADER_STAGES] = { 0, }; uint32_t buffer_view_count = 0; uint32_t dynamic_offset_count = 0; @@ -183,18 +228,21 @@ VkResult anv_CreateDescriptorSetLayout( #ifndef NDEBUG set_layout->binding[b].type = binding->descriptorType; #endif + set_layout->binding[b].data = + anv_descriptor_data_for_type(&device->instance->physicalDevice, + binding->descriptorType); set_layout->binding[b].array_size = binding->descriptorCount; set_layout->binding[b].descriptor_index = set_layout->size; set_layout->size += binding->descriptorCount; + if (set_layout->binding[b].data & ANV_DESCRIPTOR_BUFFER_VIEW) { + set_layout->binding[b].buffer_view_index = buffer_view_count; + buffer_view_count += binding->descriptorCount; + } + switch (binding->descriptorType) { case VK_DESCRIPTOR_TYPE_SAMPLER: case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: - anv_foreach_stage(s, binding->stageFlags) { - set_layout->binding[b].stage[s].sampler_index = sampler_count[s]; - sampler_count[s] += binding->descriptorCount; - } - if (binding->pImmutableSamplers) { set_layout->binding[b].immutable_samplers = samplers; samplers += binding->descriptorCount; @@ -208,51 +256,13 @@ VkResult anv_CreateDescriptorSetLayout( break; } - switch (binding->descriptorType) { - case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: - case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: - set_layout->binding[b].buffer_view_index = buffer_view_count; - buffer_view_count += binding->descriptorCount; - /* fall through */ - - case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: - case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: - case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: - case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: - case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: - case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: - case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: - case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: - anv_foreach_stage(s, binding->stageFlags) { - set_layout->binding[b].stage[s].surface_index = surface_count[s]; - surface_count[s] += binding->descriptorCount; - } - break; - default: - break; - } - switch (binding->descriptorType) { case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: set_layout->binding[b].dynamic_offset_index = dynamic_offset_count; dynamic_offset_count += binding->descriptorCount; break; - default: - break; - } - switch (binding->descriptorType) { - case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: - case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: - if (device->info.gen < 9) { - anv_foreach_stage(s, binding->stageFlags) { - set_layout->binding[b].stage[s].image_param_index = - image_param_count[s]; - image_param_count[s] += binding->descriptorCount; - } - } - break; default: break; } @@ -300,11 +310,11 @@ static void sha1_update_descriptor_set_binding_layout(struct mesa_sha1 *ctx, const struct anv_descriptor_set_binding_layout *layout) { + SHA1_UPDATE_VALUE(ctx, layout->data); SHA1_UPDATE_VALUE(ctx, layout->array_size); SHA1_UPDATE_VALUE(ctx, layout->descriptor_index); SHA1_UPDATE_VALUE(ctx, layout->dynamic_offset_index); SHA1_UPDATE_VALUE(ctx, layout->buffer_view_index); - _mesa_sha1_update(ctx, layout->stage, sizeof(layout->stage)); if (layout->immutable_samplers) { for (uint16_t i = 0; i < layout->array_size; i++) @@ -351,7 +361,6 @@ VkResult anv_CreatePipelineLayout( unsigned dynamic_offset_count = 0; - memset(layout->stage, 0, sizeof(layout->stage)); for (uint32_t set = 0; set < pCreateInfo->setLayoutCount; set++) { ANV_FROM_HANDLE(anv_descriptor_set_layout, set_layout, pCreateInfo->pSetLayouts[set]); @@ -364,10 +373,6 @@ VkResult anv_CreatePipelineLayout( continue; dynamic_offset_count += set_layout->binding[b].array_size; - for (gl_shader_stage s = 0; s < MESA_SHADER_STAGES; s++) { - if (set_layout->binding[b].stage[s].surface_index >= 0) - layout->stage[s].has_dynamic_offsets = true; - } } } @@ -379,10 +384,6 @@ VkResult anv_CreatePipelineLayout( sizeof(layout->set[s].dynamic_offset_start)); } _mesa_sha1_update(&ctx, &layout->num_sets, sizeof(layout->num_sets)); - for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) { - _mesa_sha1_update(&ctx, &layout->stage[s].has_dynamic_offsets, - sizeof(layout->stage[s].has_dynamic_offsets)); - } _mesa_sha1_final(&ctx, layout->sha1); *pPipelineLayout = anv_pipeline_layout_to_handle(layout); @@ -433,14 +434,14 @@ VkResult anv_CreateDescriptorPool( uint32_t descriptor_count = 0; uint32_t buffer_view_count = 0; for (uint32_t i = 0; i < pCreateInfo->poolSizeCount; i++) { - switch (pCreateInfo->pPoolSizes[i].type) { - case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: - case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: + enum anv_descriptor_data desc_data = + anv_descriptor_data_for_type(&device->instance->physicalDevice, + pCreateInfo->pPoolSizes[i].type); + + if (desc_data & ANV_DESCRIPTOR_BUFFER_VIEW) buffer_view_count += pCreateInfo->pPoolSizes[i].descriptorCount; - default: - descriptor_count += pCreateInfo->pPoolSizes[i].descriptorCount; - break; - } + + descriptor_count += pCreateInfo->pPoolSizes[i].descriptorCount; } const size_t pool_size = @@ -812,6 +813,7 @@ anv_descriptor_set_write_buffer(struct anv_device *device, .range = range, }; } else { + assert(bind_layout->data & ANV_DESCRIPTOR_BUFFER_VIEW); struct anv_buffer_view *bview = &set->buffer_views[bind_layout->buffer_view_index + element]; diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index 889d58aa84c..c528132d9ca 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -444,8 +444,6 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice, struct brw_stage_prog_data *prog_data, struct anv_pipeline_bind_map *map) { - gl_shader_stage stage = shader->info.stage; - struct apply_pipeline_layout_state state = { .shader = shader, .layout = layout, @@ -487,7 +485,10 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice, struct anv_descriptor_set_binding_layout *binding = &set_layout->binding[b]; - if (binding->stage[stage].surface_index >= 0) { + if (binding->array_size == 0) + continue; + + if (binding->data & ANV_DESCRIPTOR_SURFACE_STATE) { state.set[set].surface_offsets[b] = map->surface_count; struct anv_sampler **samplers = binding->immutable_samplers; for (unsigned i = 0; i < binding->array_size; i++) { @@ -504,7 +505,7 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice, } } - if (binding->stage[stage].sampler_index >= 0) { + if (binding->data & ANV_DESCRIPTOR_SAMPLER_STATE) { state.set[set].sampler_offsets[b] = map->sampler_count; struct anv_sampler **samplers = binding->immutable_samplers; for (unsigned i = 0; i < binding->array_size; i++) { @@ -521,7 +522,7 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice, } } - if (binding->stage[stage].image_param_index >= 0) { + if (binding->data & ANV_DESCRIPTOR_IMAGE_PARAM) { state.set[set].image_offsets[b] = map->image_param_count; map->image_param_count += binding->array_size; } diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index f00061c711d..0573b99bab6 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1498,12 +1498,26 @@ struct anv_vue_header { float PointWidth; }; +enum anv_descriptor_data { + /** The descriptor contains a BTI reference to a surface state */ + ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0), + /** The descriptor contains a BTI reference to a sampler state */ + ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1), + /** The descriptor contains an actual buffer view */ + ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2), + /** The descriptor contains auxiliary image layout data */ + ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3), +}; + struct anv_descriptor_set_binding_layout { #ifndef NDEBUG /* The type of the descriptors in this binding */ VkDescriptorType type; #endif + /* Bitfield representing the type of data this descriptor contains */ + enum anv_descriptor_data data; + /* Number of array elements in this binding */ uint16_t array_size; @@ -1516,17 +1530,6 @@ struct anv_descriptor_set_binding_layout { /* Index into the descriptor set buffer views */ int16_t buffer_view_index; - struct { - /* Index into the binding table for the associated surface */ - int16_t surface_index; - - /* Index into the sampler table for the associated sampler */ - int16_t sampler_index; - - /* Index into the image param table for the associated image */ - int16_t image_param_index; - } stage[MESA_SHADER_STAGES]; - /* Immutable samplers (or NULL if no immutable samplers) */ struct anv_sampler **immutable_samplers; }; @@ -1756,10 +1759,6 @@ struct anv_pipeline_layout { uint32_t num_sets; - struct { - bool has_dynamic_offsets; - } stage[MESA_SHADER_STAGES]; - unsigned char sha1[20]; };