radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE
Two more little piglits. NOTE: This is a candidate for the 9.1 branch.
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2eac0aa1d8
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4730dea5f5
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@ -140,7 +140,6 @@ struct r600_context {
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unsigned pa_sc_line_stipple;
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unsigned pa_su_sc_mode_cntl;
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unsigned pa_cl_clip_cntl;
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unsigned pa_cl_vs_out_cntl;
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/* for saving when using blitter */
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struct pipe_stencil_ref stencil_ref;
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struct si_pipe_shader_selector *ps_shader;
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@ -612,7 +612,9 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
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/* Select the correct target */
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switch(d->Semantic.Name) {
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case TGSI_SEMANTIC_PSIZE:
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target = V_008DFC_SQ_EXP_POS;
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shader->vs_out_misc_write = 1;
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shader->vs_out_point_size = 1;
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target = V_008DFC_SQ_EXP_POS + 1;
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break;
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case TGSI_SEMANTIC_POSITION:
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if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
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@ -110,6 +110,8 @@ struct si_shader {
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bool uses_kill;
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bool uses_instanceid;
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bool fs_write_all;
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bool vs_out_misc_write;
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bool vs_out_point_size;
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unsigned nr_cbufs;
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};
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@ -412,9 +412,6 @@ static void *si_create_rs_state(struct pipe_context *ctx,
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S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
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S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
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S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
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rs->pa_cl_vs_out_cntl =
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S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
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S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
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clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
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@ -485,7 +482,6 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
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rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
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rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
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rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
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rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
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si_pm4_bind_state(rctx, rasterizer, rs);
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si_update_fb_rs_state(rctx);
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@ -55,8 +55,13 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
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* takes care of adding a dummy export.
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*/
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for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
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if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
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switch (shader->shader.output[i].name) {
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case TGSI_SEMANTIC_POSITION:
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case TGSI_SEMANTIC_PSIZE:
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break;
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default:
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nparams++;
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}
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}
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if (nparams < 1)
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nparams = 1;
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@ -66,7 +71,9 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
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si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
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S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
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S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
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S_02870C_POS1_EXPORT_FORMAT(shader->shader.vs_out_misc_write ?
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V_02870C_SPI_SHADER_4COMP :
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V_02870C_SPI_SHADER_NONE) |
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S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
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S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
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@ -261,6 +268,7 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
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const struct pipe_draw_info *info)
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{
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struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
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struct si_shader *vs = &rctx->vs_shader->current->shader;
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unsigned prim = si_conv_pipe_prim(info->mode);
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unsigned ls_mask = 0;
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@ -297,7 +305,8 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
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si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
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}
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si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
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prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
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S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
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S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write)
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/*| (rctx->rasterizer->clip_plane_enable &
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rctx->vs_shader->shader.clip_dist_write)*/);
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si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
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