radeonsi: provide VS_STATE input to all VS variants
v2: fix incorrect change in get_tcs_out_patch_stride Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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3b9fbcb3b6
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472c84d1ad
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@ -1835,8 +1835,12 @@ static void si_set_user_data_base(struct si_context *sctx,
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if (*base != new_base) {
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*base = new_base;
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if (new_base)
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if (new_base) {
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si_mark_shader_pointers_dirty(sctx, shader);
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if (shader == PIPE_SHADER_VERTEX)
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sctx->last_vs_state = ~0;
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}
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}
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}
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@ -227,7 +227,7 @@ static LLVMValueRef
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get_tcs_in_patch_stride(struct si_shader_context *ctx)
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{
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if (ctx->type == PIPE_SHADER_VERTEX)
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return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 8, 13);
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return unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 8, 13);
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else if (ctx->type == PIPE_SHADER_TESS_CTRL)
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return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 8, 13);
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else {
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@ -2663,7 +2663,7 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
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LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
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ctx->param_rel_auto_id);
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LLVMValueRef vertex_dw_stride =
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unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 24, 8);
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unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 24, 8);
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LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
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vertex_dw_stride, "");
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@ -5609,19 +5609,16 @@ static void create_function(struct si_shader_context *ctx)
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params[SI_PARAM_BASE_VERTEX] = ctx->i32;
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params[SI_PARAM_START_INSTANCE] = ctx->i32;
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params[SI_PARAM_DRAWID] = ctx->i32;
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num_params = SI_PARAM_DRAWID+1;
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params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
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num_params = SI_PARAM_VS_STATE_BITS+1;
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if (shader->key.as_es) {
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params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
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} else if (shader->key.as_ls) {
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params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
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num_params = SI_PARAM_LS_OUT_LAYOUT+1;
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/* no extra parameters */
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} else {
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if (shader->is_gs_copy_shader) {
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num_params = SI_PARAM_RW_BUFFERS+1;
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} else {
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params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
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num_params = SI_PARAM_VS_STATE_BITS+1;
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}
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/* The locations of the other parameters are assigned dynamically. */
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@ -98,16 +98,9 @@ enum {
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SI_SGPR_BASE_VERTEX,
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SI_SGPR_START_INSTANCE,
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SI_SGPR_DRAWID,
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SI_ES_NUM_USER_SGPR,
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/* hw VS only */
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SI_SGPR_VS_STATE_BITS = SI_ES_NUM_USER_SGPR,
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SI_SGPR_VS_STATE_BITS,
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SI_VS_NUM_USER_SGPR,
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/* hw LS only */
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SI_SGPR_LS_OUT_LAYOUT = SI_ES_NUM_USER_SGPR,
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SI_LS_NUM_USER_SGPR,
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/* both TCS and TES */
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SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
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SI_TES_NUM_USER_SGPR,
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@ -146,11 +139,7 @@ enum {
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SI_PARAM_BASE_VERTEX,
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SI_PARAM_START_INSTANCE,
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SI_PARAM_DRAWID,
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/* [0] = clamp vertex color, VS as VS only */
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SI_PARAM_VS_STATE_BITS,
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/* same value as TCS_IN_LAYOUT, VS as LS only */
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SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_DRAWID + 1,
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/* the other VS parameters are assigned dynamically */
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/* Layout of TCS outputs in the offchip buffer
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* [0:8] = the number of patches per threadgroup.
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@ -222,9 +222,9 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
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(num_tcs_output_cp << 9) | *num_patches;
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/* Set them for LS. */
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radeon_set_sh_reg(cs,
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R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
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tcs_in_layout);
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sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
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C_VS_STATE_LS_OUT_VERTEX_SIZE;
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sctx->current_vs_state |= tcs_in_layout;
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/* Set them for TCS. */
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radeon_set_sh_reg_seq(cs,
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@ -500,7 +500,8 @@ static void si_emit_vs_state(struct si_context *sctx)
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struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
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radeon_set_sh_reg(cs,
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R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_VS_STATE_BITS * 4,
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sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] +
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SI_SGPR_VS_STATE_BITS * 4,
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sctx->current_vs_state);
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sctx->last_vs_state = sctx->current_vs_state;
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@ -464,7 +464,7 @@ static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
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S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
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S_00B528_DX10_CLAMP(1) |
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S_00B528_FLOAT_MODE(shader->config.float_mode);
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shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
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shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
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S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
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}
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@ -512,7 +512,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
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if (shader->selector->type == PIPE_SHADER_VERTEX) {
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vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
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num_user_sgprs = SI_ES_NUM_USER_SGPR;
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num_user_sgprs = SI_VS_NUM_USER_SGPR;
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} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
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vgpr_comp_cnt = 3; /* all components are needed for TES */
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num_user_sgprs = SI_TES_NUM_USER_SGPR;
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