svga: Fix typos in comments.
Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7943>
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@ -1113,7 +1113,7 @@ SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
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*
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* A query will be identified by the gmrId and offset of the guestResult
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* member. If the device can't find an SVGA_3D_CMD_END_QUERY that has
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* been sent previously with an indentical gmrId and offset, it will
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* been sent previously with an identical gmrId and offset, it will
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* effectively end all queries with an identical type issued with the
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* same cid, and the SVGA3dQueryResult structure pointed to by
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* guestResult will not be written to. This property can be used to
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@ -273,7 +273,7 @@ typedef enum {
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* If this cap is present, the provokingVertexLast field in the
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* rasterizer state is enabled. (Guests can then set it to FALSE,
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* meaning that the first vertex is the provoking vertex, or TRUE,
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* meaning that the last verteix is the provoking vertex.)
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* meaning that the last vertex is the provoking vertex.)
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*
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* If this cap is FALSE, then guests should set the provokingVertexLast
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* to FALSE, otherwise rendering behavior is undefined.
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@ -614,7 +614,7 @@ struct {
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* reused.
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*
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* SVGA_CAP_CMD_BUFFERS_2 --
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* Enable support for the prepend command buffer submision
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* Enable support for the prepend command buffer submission
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* registers. SVGA_REG_CMD_PREPEND_LOW and
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* SVGA_REG_CMD_PREPEND_HIGH.
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*
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@ -877,7 +877,7 @@ enum {
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*
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* 1. If the guest wishes to fully sync (drain) the FIFO,
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* it will write once to SYNC then poll on the BUSY
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* register. The FIFO is sync'ed once BUSY is zero.
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* register. The FIFO is synced once BUSY is zero.
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*
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* 2. If the guest wants to asynchronously wake up the host,
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* it will write once to SYNC without polling on BUSY.
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@ -1205,7 +1205,7 @@ typedef struct SVGADisplayTopology {
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* memory must come from the GFB. The guest is not allowed to
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* access the memory and doing so will have undefined results. The
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* backing store is required to be page aligned and the size is
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* padded to the next page boundry. The number of pages is:
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* padded to the next page boundary. The number of pages is:
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* (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
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*
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* The pitch in the backingStore is required to be at least large
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@ -1777,7 +1777,7 @@ struct {
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* identically-sized region on the same or a different screen.
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*
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* Note that the source pixels for the COPY in this annotation are
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* sampled before applying the anqnotation's associated blit. They
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* sampled before applying the annotation's associated blit. They
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* are allowed to overlap with the blit's destination pixels.
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*
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* The copy source rectangle is specified the same way as the blit
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@ -505,7 +505,7 @@ struct svga_context
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/* Bitmask of depth/stencil state objects IDs */
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struct util_bitmask *ds_object_id_bm;
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/* Bitmaks of input element object IDs */
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/* Bitmask of input element object IDs */
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struct util_bitmask *input_element_object_id_bm;
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/* Bitmask of rasterizer object IDs */
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@ -1279,7 +1279,7 @@ svga_render_condition(struct pipe_context *pipe, struct pipe_query *q,
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/*
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* This function is a workaround because we lack the ability to query
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* renderer's time synchornously.
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* renderer's time synchronously.
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*/
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static uint64_t
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svga_get_timestamp(struct pipe_context *pipe)
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@ -490,7 +490,7 @@ svga_set_stream_output_targets(struct pipe_context *pipe,
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if (svga_have_sm5(svga) && svga->current_so && begin_so_queries) {
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/* If there are aleady active queries and we need to start a new streamout,
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/* If there are already active queries and we need to start a new streamout,
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* we need to stop the current active queries first.
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*/
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if (svga->in_streamout) {
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@ -116,7 +116,7 @@ svga_create_vs_state(struct pipe_context *pipe,
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tgsi_scan_shader(vs->base.tokens, &vs->base.info);
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{
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/* Need to do construct a new template in case we substitued a
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/* Need to do construct a new template in case we substituted a
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* debug shader.
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*/
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struct pipe_shader_state tmp2 = *templ;
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@ -841,7 +841,7 @@ emit_constbuf_vgpu10(struct svga_context *svga, enum pipe_shader_type shader)
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size = align(size, 16);
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}
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else {
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/* round down to mulitple of 16 (this may cause rendering problems
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/* round down to multiple of 16 (this may cause rendering problems
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* but should avoid a device error).
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*/
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size &= ~15;
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@ -541,7 +541,7 @@ svga_validate_surface_view(struct svga_context *svga, struct svga_surface *s)
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/**
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* DX spec explicitly specifies that no resource can be bound to a render
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* target view and a shader resource view simultanously.
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* target view and a shader resource view simultaneously.
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* So first check if the resource bound to this surface view collides with
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* a sampler view. If so, then we will clone this surface view and its
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* associated resource. We will then use the cloned surface view for
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@ -2387,7 +2387,7 @@ emit_lit(struct svga_shader_emitter *emit,
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return emit_simple_instruction(emit, SVGA3DOP_LIT, insn);
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}
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else {
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/* D3D vs. GL semantics can be fairly easily accomodated by
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/* D3D vs. GL semantics can be fairly easily accommodated by
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* variations on this sequence.
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*
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* GL:
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@ -400,7 +400,7 @@ struct svga_winsys_context
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* Map a guest-backed surface.
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* \param swc The winsys context
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* \param surface The surface to map
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* \param flags bitmaks of PIPE_MAP_x flags
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* \param flags bitmask of PIPE_MAP_x flags
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* \param retry Whether to flush and retry the map
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* \param rebind Whether to issue an immediate rebind and flush.
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*
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@ -791,7 +791,7 @@ struct svga_winsys_screen
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/** Have SM5 hardware? */
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boolean have_sm5;
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/** To rebind resources at the beginnning of a new command buffer */
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/** To rebind resources at the beginning of a new command buffer */
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boolean need_to_rebind_resources;
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boolean have_generate_mipmap_cmd;
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