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i965: Add do32 debug option. 

The do32 INTEL_DEBUG option causes the back-end to try to generate a
SIMD32 program when compiling a compute shader regardless of the
specified compute shader workgroup size, which will be useful for
testing SIMD32 code generation in the most common case in which the
workgroup size doesn't exceed the SIMD16 limit so SIMD32 codegen
wouldn't be automatically enabled.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Francisco Jerez 2016-05-26 21:28:45 -07:00
parent 864737ce6c
commit 46ce93ed22
3 changed files with 3 additions and 1 deletions
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2
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@ -6528,7 +6528,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
NULL, /* Never used in core profile */
shader, 32, shader_time_index);
if (!fail_msg && v8.max_dispatch_width >= 32 &&
simd_required > 16) {
(simd_required > 16 || (INTEL_DEBUG & DEBUG_DO32))) {
/* Try a SIMD32 compile */
if (simd_required <= 8)
v32.import_uniforms(&v8);

1
src/mesa/drivers/dri/i965/intel_debug.c
View File

@ -79,6 +79,7 @@ static const struct debug_control debug_control[] = {
{ "ds", DEBUG_TES },
{ "tes", DEBUG_TES },
{ "l3", DEBUG_L3 },
{ "do32", DEBUG_DO32 },
{ NULL, 0 }
};

1
src/mesa/drivers/dri/i965/intel_debug.h
View File

@ -72,6 +72,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_TCS (1ull << 36)
#define DEBUG_TES (1ull << 37)
#define DEBUG_L3 (1ull << 38)
#define DEBUG_DO32 (1ull << 39)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"