radeon/uvd:add uvd hevc enc hw interface header
Add hevc encode hardware interface for UVD Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
This commit is contained in:
parent
c6acae22c8
commit
461508c15c
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@ -15,6 +15,7 @@ C_SOURCES := \
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radeon_vcn_enc_1_2.c \
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radeon_vcn_enc_1_2.c \
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radeon_vcn_enc.c \
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radeon_vcn_enc.c \
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radeon_vcn_enc.h \
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radeon_vcn_enc.h \
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radeon_uvd_enc.h \
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radeon_vce_40_2_2.c \
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radeon_vce_40_2_2.c \
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radeon_vce_50.c \
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radeon_vce_50.c \
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radeon_vce_52.c \
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radeon_vce_52.c \
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@ -35,6 +35,7 @@ files_libradeon = files(
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'radeon_vcn_enc.h',
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'radeon_vcn_enc.h',
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'radeon_vcn_dec.c',
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'radeon_vcn_dec.c',
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'radeon_vcn_dec.h',
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'radeon_vcn_dec.h',
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'radeon_uvd_enc.h',
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'radeon_vce_40_2_2.c',
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'radeon_vce_40_2_2.c',
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'radeon_vce_50.c',
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'radeon_vce_50.c',
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'radeon_vce_52.c',
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'radeon_vce_52.c',
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@ -0,0 +1,469 @@
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/**************************************************************************
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*
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* Copyright 2018 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#ifndef _RADEON_UVD_ENC_H
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#define _RADEON_UVD_ENC_H
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#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
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#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
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#define RENC_UVD_IB_PARAM_SESSION_INFO 0x00000001
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#define RENC_UVD_IB_PARAM_TASK_INFO 0x00000002
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#define RENC_UVD_IB_PARAM_SESSION_INIT 0x00000003
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#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x00000004
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#define RENC_UVD_IB_PARAM_LAYER_SELECT 0x00000005
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#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x00000006
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#define RENC_UVD_IB_PARAM_SPEC_MISC 0x00000007
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#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000008
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#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000009
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#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x0000000a
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#define RENC_UVD_IB_PARAM_SLICE_HEADER 0x0000000b
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#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x0000000c
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#define RENC_UVD_IB_PARAM_QUALITY_PARAMS 0x0000000d
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#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x0000000e
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#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x0000000f
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#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000010
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#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000011
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#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER 0x00000012
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#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER 0x00000013
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#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL 0x00000014
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#define RENC_UVD_IB_OP_INITIALIZE 0x08000001
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#define RENC_UVD_IB_OP_CLOSE_SESSION 0x08000002
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#define RENC_UVD_IB_OP_ENCODE 0x08000003
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#define RENC_UVD_IB_OP_INIT_RC 0x08000004
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#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x08000005
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#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE 0x08000006
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#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE 0x08000007
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#define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE 0x08000008
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#define RENC_UVD_IF_MAJOR_VERSION_MASK 0xFFFF0000
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#define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
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#define RENC_UVD_IF_MINOR_VERSION_MASK 0x0000FFFF
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#define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
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#define RENC_UVD_PREENCODE_MODE_NONE 0x00000000
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#define RENC_UVD_PREENCODE_MODE_1X 0x00000001
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#define RENC_UVD_PREENCODE_MODE_2X 0x00000002
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#define RENC_UVD_PREENCODE_MODE_4X 0x00000004
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#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
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#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
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#define RENC_UVD_RATE_CONTROL_METHOD_NONE 0x00000000
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#define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
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#define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002
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#define RENC_UVD_RATE_CONTROL_METHOD_CBR 0x00000003
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#define RENC_UVD_NALU_TYPE_AUD 0x00000001
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#define RENC_UVD_NALU_TYPE_VPS 0x00000002
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#define RENC_UVD_NALU_TYPE_SPS 0x00000003
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#define RENC_UVD_NALU_TYPE_PPS 0x00000004
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#define RENC_UVD_NALU_TYPE_END_OF_SEQUENCE 0x00000005
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#define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16
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#define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16
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#define RENC_UVD_HEADER_INSTRUCTION_END 0
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#define RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 1
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#define RENC_UVD_HEADER_INSTRUCTION_COPY 2
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#define RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE 3
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#define RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT 4
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#define RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA 5
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#define RENC_UVD_PICTURE_TYPE_B 0
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#define RENC_UVD_PICTURE_TYPE_P 1
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#define RENC_UVD_PICTURE_TYPE_I 2
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#define RENC_UVD_PICTURE_TYPE_P_SKIP 3
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#define RENC_UVD_SWIZZLE_MODE_LINEAR 0
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#define RENC_UVD_SWIZZLE_MODE_256B_D 2
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#define RENC_UVD_SWIZZLE_MODE_4kB_D 6
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#define RENC_UVD_SWIZZLE_MODE_64kB_D 10
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#define RENC_UVD_INTRA_REFRESH_MODE_NONE 0
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#define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_ROWS 1
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#define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2
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#define RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES 34
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#define RENC_UVD_ADDR_MODE_LINEAR 0
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#define RENC_UVD_ADDR_MODE_PELE_8X8_1D 1
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#define RENC_UVD_ADDR_MODE_32AS8_88 2
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#define RENC_UVD_ARRAY_MODE_LINEAR 0
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#define RENC_UVD_ARRAY_MODE_PELE_8X8_1D 2
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#define RENC_UVD_ARRAY_MODE_2D_TILED_THIN1 4
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#define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0
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#define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1
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#define RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR 0
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#define RENC_UVD_FEEDBACK_BUFFER_MODE_CIRCULAR 1
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#define RENC_UVD_FEEDBACK_STATUS_OK 0x00000000
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#define RENC_UVD_FEEDBACK_STATUS_NOT_ENCODED 0x10000001
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typedef struct radeon_uvd_enc_feedback_s
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{
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uint32_t task_id;
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uint32_t first_in_task;
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uint32_t last_in_task;
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uint32_t status;
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uint32_t has_bitstream;
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uint32_t bitstream_offset;
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uint32_t bitstream_size;
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uint32_t enabled_filler_data;
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uint32_t filler_data_size;
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uint32_t extra_bytes;
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} radeon_uvd_enc_feedback_t;
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typedef struct ruvd_enc_session_info_s
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{
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uint32_t reserved;
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uint32_t interface_version;
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uint32_t sw_context_address_hi;
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uint32_t sw_context_address_lo;
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} ruvd_enc_session_info_t;
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typedef struct ruvd_enc_task_info_s
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{
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uint32_t total_size_of_all_packages;
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uint32_t task_id;
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uint32_t allowed_max_num_feedbacks;
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} ruvd_enc_task_info_t;
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typedef struct ruvd_enc_session_init_s
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{
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uint32_t aligned_picture_width;
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uint32_t aligned_picture_height;
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uint32_t padding_width;
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uint32_t padding_height;
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uint32_t pre_encode_mode;
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uint32_t pre_encode_chroma_enabled;
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} ruvd_enc_session_init_t;
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typedef struct ruvd_enc_layer_control_s
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{
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uint32_t max_num_temporal_layers;
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uint32_t num_temporal_layers;
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} ruvd_enc_layer_control_t;
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typedef struct ruvd_enc_layer_select_s
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{
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uint32_t temporal_layer_index;
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} ruvd_enc_layer_select_t;
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typedef struct ruvd_enc_hevc_slice_control_s
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{
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uint32_t slice_control_mode;
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union
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{
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struct
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{
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uint32_t num_ctbs_per_slice;
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uint32_t num_ctbs_per_slice_segment;
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} fixed_ctbs_per_slice;
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struct
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{
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uint32_t num_bits_per_slice;
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uint32_t num_bits_per_slice_segment;
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} fixed_bits_per_slice;
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};
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} ruvd_enc_hevc_slice_control_t;
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typedef struct ruvd_enc_hevc_spec_misc_s
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{
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uint32_t log2_min_luma_coding_block_size_minus3;
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uint32_t amp_disabled;
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uint32_t strong_intra_smoothing_enabled;
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uint32_t constrained_intra_pred_flag;
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uint32_t cabac_init_flag;
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uint32_t half_pel_enabled;
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uint32_t quarter_pel_enabled;
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} ruvd_enc_hevc_spec_misc_t;
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typedef struct ruvd_enc_rate_ctl_session_init_s
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{
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uint32_t rate_control_method;
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uint32_t vbv_buffer_level;
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} ruvd_enc_rate_ctl_session_init_t;
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typedef struct ruvd_enc_rate_ctl_layer_init_s
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{
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uint32_t target_bit_rate;
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uint32_t peak_bit_rate;
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uint32_t frame_rate_num;
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uint32_t frame_rate_den;
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uint32_t vbv_buffer_size;
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uint32_t avg_target_bits_per_picture;
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uint32_t peak_bits_per_picture_integer;
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uint32_t peak_bits_per_picture_fractional;
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} ruvd_enc_rate_ctl_layer_init_t;
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typedef struct ruvd_enc_rate_ctl_per_picture_s
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{
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uint32_t qp;
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uint32_t min_qp_app;
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uint32_t max_qp_app;
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uint32_t max_au_size;
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uint32_t enabled_filler_data;
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uint32_t skip_frame_enable;
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uint32_t enforce_hrd;
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} ruvd_enc_rate_ctl_per_picture_t;
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typedef struct ruvd_enc_quality_params_s
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{
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uint32_t vbaq_mode;
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uint32_t scene_change_sensitivity;
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uint32_t scene_change_min_idr_interval;
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} ruvd_enc_quality_params_t;
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typedef struct ruvd_enc_direct_output_nalu_s
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{
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uint32_t type;
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uint32_t size;
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uint32_t data[1];
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} ruvd_enc_direct_output_nalu_t;
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typedef struct ruvd_enc_slice_header_s
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{
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uint32_t
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bitstream_template
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[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
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struct
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{
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uint32_t instruction;
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uint32_t num_bits;
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} instructions[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
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} ruvd_enc_slice_header_t;
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typedef struct ruvd_enc_encode_params_s
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{
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uint32_t pic_type;
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uint32_t allowed_max_bitstream_size;
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uint32_t input_picture_luma_address_hi;
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uint32_t input_picture_luma_address_lo;
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uint32_t input_picture_chroma_address_hi;
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uint32_t input_picture_chroma_address_lo;
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uint32_t input_pic_luma_pitch;
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uint32_t input_pic_chroma_pitch;
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union
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{
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uint32_t input_pic_addr_mode;
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uint32_t reserved;
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};
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union
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{
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uint32_t input_pic_array_mode;
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uint32_t input_pic_swizzle_mode;
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};
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uint32_t reference_picture_index;
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uint32_t reconstructed_picture_index;
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} ruvd_enc_encode_params_t;
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typedef struct ruvd_enc_hevc_deblocking_filter_s
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{
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uint32_t loop_filter_across_slices_enabled;
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int32_t deblocking_filter_disabled;
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int32_t beta_offset_div2;
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int32_t tc_offset_div2;
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int32_t cb_qp_offset;
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int32_t cr_qp_offset;
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} ruvd_enc_hevc_deblocking_filter_t;
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typedef struct ruvd_enc_intra_refresh_s
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{
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uint32_t intra_refresh_mode;
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uint32_t offset;
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uint32_t region_size;
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} ruvd_enc_intra_refresh_t;
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typedef struct ruvd_enc_reconstructed_picture_s
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{
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uint32_t luma_offset;
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uint32_t chroma_offset;
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} ruvd_enc_reconstructed_picture_t;
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typedef struct ruvd_enc_encode_context_buffer_s
|
||||||
|
{
|
||||||
|
uint32_t encode_context_address_hi;
|
||||||
|
uint32_t encode_context_address_lo;
|
||||||
|
union
|
||||||
|
{
|
||||||
|
uint32_t addr_mode;
|
||||||
|
uint32_t reserved;
|
||||||
|
};
|
||||||
|
union
|
||||||
|
{
|
||||||
|
uint32_t array_mode;
|
||||||
|
uint32_t swizzle_mode;
|
||||||
|
};
|
||||||
|
uint32_t rec_luma_pitch;
|
||||||
|
uint32_t rec_chroma_pitch;
|
||||||
|
uint32_t num_reconstructed_pictures;
|
||||||
|
ruvd_enc_reconstructed_picture_t
|
||||||
|
reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
|
||||||
|
uint32_t pre_encode_picture_luma_pitch;
|
||||||
|
uint32_t pre_encode_picture_chroma_pitch;
|
||||||
|
ruvd_enc_reconstructed_picture_t
|
||||||
|
pre_encode_reconstructed_pictures
|
||||||
|
[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
|
||||||
|
ruvd_enc_reconstructed_picture_t pre_encode_input_picture;
|
||||||
|
} ruvd_enc_encode_context_buffer_t;
|
||||||
|
|
||||||
|
typedef struct ruvd_enc_video_bitstream_buffer_s
|
||||||
|
{
|
||||||
|
uint32_t mode;
|
||||||
|
uint32_t video_bitstream_buffer_address_hi;
|
||||||
|
uint32_t video_bitstream_buffer_address_lo;
|
||||||
|
uint32_t video_bitstream_buffer_size;
|
||||||
|
uint32_t video_bitstream_data_offset;
|
||||||
|
} ruvd_enc_video_bitstream_buffer_t;
|
||||||
|
|
||||||
|
typedef struct ruvd_enc_feedback_buffer_s
|
||||||
|
{
|
||||||
|
uint32_t mode;
|
||||||
|
uint32_t feedback_buffer_address_hi;
|
||||||
|
uint32_t feedback_buffer_address_lo;
|
||||||
|
uint32_t feedback_buffer_size;
|
||||||
|
uint32_t feedback_data_size;
|
||||||
|
} ruvd_enc_feedback_buffer_t;
|
||||||
|
|
||||||
|
typedef void (*radeon_uvd_enc_get_buffer) (struct pipe_resource * resource,
|
||||||
|
struct pb_buffer ** handle,
|
||||||
|
struct radeon_surf ** surface);
|
||||||
|
|
||||||
|
struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context
|
||||||
|
*context,
|
||||||
|
const struct
|
||||||
|
pipe_video_codec *templat,
|
||||||
|
struct radeon_winsys *ws,
|
||||||
|
radeon_uvd_enc_get_buffer
|
||||||
|
get_buffer);
|
||||||
|
|
||||||
|
struct radeon_uvd_enc_pic
|
||||||
|
{
|
||||||
|
enum pipe_h265_enc_picture_type picture_type;
|
||||||
|
|
||||||
|
unsigned frame_num;
|
||||||
|
unsigned pic_order_cnt;
|
||||||
|
unsigned pic_order_cnt_type;
|
||||||
|
unsigned crop_left;
|
||||||
|
unsigned crop_right;
|
||||||
|
unsigned crop_top;
|
||||||
|
unsigned crop_bottom;
|
||||||
|
unsigned general_tier_flag;
|
||||||
|
unsigned general_profile_idc;
|
||||||
|
unsigned general_level_idc;
|
||||||
|
unsigned max_poc;
|
||||||
|
unsigned log2_max_poc;
|
||||||
|
unsigned chroma_format_idc;
|
||||||
|
unsigned pic_width_in_luma_samples;
|
||||||
|
unsigned pic_height_in_luma_samples;
|
||||||
|
unsigned log2_diff_max_min_luma_coding_block_size;
|
||||||
|
unsigned log2_min_transform_block_size_minus2;
|
||||||
|
unsigned log2_diff_max_min_transform_block_size;
|
||||||
|
unsigned max_transform_hierarchy_depth_inter;
|
||||||
|
unsigned max_transform_hierarchy_depth_intra;
|
||||||
|
unsigned log2_parallel_merge_level_minus2;
|
||||||
|
unsigned bit_depth_luma_minus8;
|
||||||
|
unsigned bit_depth_chroma_minus8;
|
||||||
|
unsigned nal_unit_type;
|
||||||
|
unsigned max_num_merge_cand;
|
||||||
|
|
||||||
|
bool not_referenced;
|
||||||
|
bool is_iframe;
|
||||||
|
bool is_even_frame;
|
||||||
|
bool sample_adaptive_offset_enabled_flag;
|
||||||
|
bool pcm_enabled_flag;
|
||||||
|
bool sps_temporal_mvp_enabled_flag;
|
||||||
|
|
||||||
|
ruvd_enc_task_info_t task_info;
|
||||||
|
ruvd_enc_session_init_t session_init;
|
||||||
|
ruvd_enc_layer_control_t layer_ctrl;
|
||||||
|
ruvd_enc_layer_select_t layer_sel;
|
||||||
|
ruvd_enc_hevc_slice_control_t hevc_slice_ctrl;
|
||||||
|
ruvd_enc_hevc_spec_misc_t hevc_spec_misc;
|
||||||
|
ruvd_enc_rate_ctl_session_init_t rc_session_init;
|
||||||
|
ruvd_enc_rate_ctl_layer_init_t rc_layer_init;
|
||||||
|
ruvd_enc_hevc_deblocking_filter_t hevc_deblock;
|
||||||
|
ruvd_enc_rate_ctl_per_picture_t rc_per_pic;
|
||||||
|
ruvd_enc_quality_params_t quality_params;
|
||||||
|
ruvd_enc_encode_context_buffer_t ctx_buf;
|
||||||
|
ruvd_enc_video_bitstream_buffer_t bit_buf;
|
||||||
|
ruvd_enc_feedback_buffer_t fb_buf;
|
||||||
|
ruvd_enc_intra_refresh_t intra_ref;
|
||||||
|
ruvd_enc_encode_params_t enc_params;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct radeon_uvd_encoder
|
||||||
|
{
|
||||||
|
struct pipe_video_codec base;
|
||||||
|
|
||||||
|
void (*begin) (struct radeon_uvd_encoder * enc,
|
||||||
|
struct pipe_picture_desc * pic);
|
||||||
|
void (*encode) (struct radeon_uvd_encoder * enc);
|
||||||
|
void (*destroy) (struct radeon_uvd_encoder * enc);
|
||||||
|
|
||||||
|
unsigned stream_handle;
|
||||||
|
|
||||||
|
struct pipe_screen *screen;
|
||||||
|
struct radeon_winsys *ws;
|
||||||
|
struct radeon_winsys_cs *cs;
|
||||||
|
|
||||||
|
radeon_uvd_enc_get_buffer get_buffer;
|
||||||
|
|
||||||
|
struct pb_buffer *handle;
|
||||||
|
struct radeon_surf *luma;
|
||||||
|
struct radeon_surf *chroma;
|
||||||
|
|
||||||
|
struct pb_buffer *bs_handle;
|
||||||
|
unsigned bs_size;
|
||||||
|
|
||||||
|
unsigned cpb_num;
|
||||||
|
|
||||||
|
struct rvid_buffer *si;
|
||||||
|
struct rvid_buffer *fb;
|
||||||
|
struct rvid_buffer cpb;
|
||||||
|
struct radeon_uvd_enc_pic enc_pic;
|
||||||
|
|
||||||
|
unsigned shifter;
|
||||||
|
unsigned bits_in_shifter;
|
||||||
|
unsigned num_zeros;
|
||||||
|
unsigned byte_index;
|
||||||
|
unsigned bits_output;
|
||||||
|
uint32_t total_task_size;
|
||||||
|
uint32_t *p_task_size;
|
||||||
|
|
||||||
|
bool emulation_prevention;
|
||||||
|
bool need_feedback;
|
||||||
|
};
|
||||||
|
|
||||||
|
void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc);
|
||||||
|
bool si_radeon_uvd_enc_supported(struct si_screen *rscreen);
|
||||||
|
|
||||||
|
#endif // _RADEON_UVD_ENC_H
|
Loading…
Reference in New Issue