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freedreno: update registers 

Pull in some updates of VSC regs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Rob Clark 2019-07-25 15:25:22 -07:00
parent c179ded9cb
commit 44f3c1cf01
2 changed files with 42 additions and 4 deletions
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33
src/freedreno/registers/a6xx.xml
View File

@ -1771,6 +1771,16 @@ to upconvert to 32b float internally?
TODO now there seem to be two buffers of VSC data (both referenced by
CP_SET_BIN_DATA packet. Not sure what this new DATA2 one is, but seems
to have the larger pitch.
The "DATA2" buffer is probably actually the main visibility stream; it
is at least the larger of the two.
For VSC_DATA_PITCH, 0x20 actually seems to be sufficient (although blob
uses something somewhat larger) for many cases, although required value
can ramp up somewhat higher. Values less than 0x20 trigger GPU hangs
even with small amount of geometry (so possibly 0x20 is minimum
alignment or something like that). So far I can't seem to find any-
thing that needs values larger than 0x20
-->
<reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
<reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
@ -1781,10 +1791,25 @@ to upconvert to 32b float internally?
<reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
<reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>
<!--
note, also a range starting at 0x0c58, one or the other probably
corresponds to the new "VSC_XXX" thing, whatever it is..
-->
<array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
<doc>
Seems to be a bitmap of which tiles mapped to the VSC
pipe contain geometry.
I suppose we can connect a maximum of 32 tiles to a
single VSC pipe.
</doc>
<reg32 offset="0x0" name="REG"/>
</array>
<array offset="0x0c58" name="VSC_SIZE2" stride="1" length="32">
<doc>
Has the size of data written to corresponding VSC_DATA2
buffer.
</doc>
<reg32 offset="0x0" name="REG"/>
</array>
<array offset="0x0c78" name="VSC_SIZE" stride="1" length="32">
<doc>
Has the size of data written to corresponding VSC pipe, ie.

13
src/freedreno/registers/adreno_pm4.xml
View File

@ -41,6 +41,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
<value name="UNK_2C" value="44" variants="A5XX"/>
<value name="UNK_2D" value="45" variants="A5XX"/>
<!-- a6xx events -->
<value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
</enum>
<enum name="pc_di_primtype">
@ -1156,5 +1159,15 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</reg32>
</domain>
<!-- I *think* this existed at least as far back as a4xx -->
<domain name="CP_COND_REG_EXEC" width="32">
<reg32 offset="0" name="0">
<bitfield name="UNK28" pos="28" type="boolean"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="DWORDS" low="0" high="31" type="uint"/>
</reg32>
</domain>
</database>