radv/ac: Implement Float64 SSBO loads.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
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@ -2148,35 +2148,58 @@ static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
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static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
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static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
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nir_intrinsic_instr *instr)
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nir_intrinsic_instr *instr)
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{
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{
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const char *load_name;
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LLVMValueRef results[2];
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LLVMTypeRef data_type = ctx->f32;
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int load_components;
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if (instr->num_components == 3)
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int num_components = instr->num_components;
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data_type = LLVMVectorType(ctx->f32, 4);
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if (instr->dest.ssa.bit_size == 64)
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else if (instr->num_components > 1)
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num_components *= 2;
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data_type = LLVMVectorType(ctx->f32, instr->num_components);
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if (instr->num_components == 4 || instr->num_components == 3)
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for (int i = 0; i < num_components; i += load_components) {
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load_name = "llvm.amdgcn.buffer.load.v4f32";
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load_components = MIN2(num_components - i, 4);
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else if (instr->num_components == 2)
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const char *load_name;
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load_name = "llvm.amdgcn.buffer.load.v2f32";
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LLVMTypeRef data_type = ctx->f32;
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else if (instr->num_components == 1)
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LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
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load_name = "llvm.amdgcn.buffer.load.f32";
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offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
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else
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abort();
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LLVMValueRef params[] = {
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if (load_components == 3)
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get_src(ctx, instr->src[0]),
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data_type = LLVMVectorType(ctx->f32, 4);
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LLVMConstInt(ctx->i32, 0, false),
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else if (load_components > 1)
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get_src(ctx, instr->src[1]),
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data_type = LLVMVectorType(ctx->f32, load_components);
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LLVMConstInt(ctx->i1, 0, false),
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LLVMConstInt(ctx->i1, 0, false),
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};
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LLVMValueRef ret =
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if (load_components >= 3)
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ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
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load_name = "llvm.amdgcn.buffer.load.v4f32";
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else if (load_components == 2)
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load_name = "llvm.amdgcn.buffer.load.v2f32";
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else if (load_components == 1)
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load_name = "llvm.amdgcn.buffer.load.f32";
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else
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unreachable("unhandled number of components");
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if (instr->num_components == 3)
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LLVMValueRef params[] = {
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ret = trim_vector(ctx, ret, 3);
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get_src(ctx, instr->src[0]),
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LLVMConstInt(ctx->i32, 0, false),
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offset,
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LLVMConstInt(ctx->i1, 0, false),
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LLVMConstInt(ctx->i1, 0, false),
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};
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results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
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}
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LLVMValueRef ret = results[0];
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if (num_components > 4 || num_components == 3) {
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LLVMValueRef masks[] = {
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LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
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LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
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LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
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LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
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};
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LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
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ret = LLVMBuildShuffleVector(ctx->builder, results[0],
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results[num_components > 4 ? 1 : 0], swizzle, "");
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}
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return LLVMBuildBitCast(ctx->builder, ret,
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return LLVMBuildBitCast(ctx->builder, ret,
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get_def_type(ctx, &instr->dest.ssa), "");
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get_def_type(ctx, &instr->dest.ssa), "");
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