freedreno/a6xx: Rename the RB_BLIT_INFO.INTEGER field to SAMPLE_0.

As @samuelig found, this is the field for disabling sample averaging and
using sample 0 instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9661>
This commit is contained in:
Eric Anholt 2021-03-17 09:43:58 -07:00 committed by Marge Bot
parent a30d091a10
commit 431b0ef9ee
3 changed files with 4 additions and 5 deletions

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@ -2126,7 +2126,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x88e3" name="RB_BLIT_INFO">
<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? -->
<bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
<bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
<bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
<bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
<doc>
For clearing depth/stencil

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@ -2383,8 +2383,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO(
.unk0 = !resolve,
.gmem = !resolve,
/* "integer" bit disables msaa resolve averaging */
.integer = vk_format_is_int(attachment->format) |
.sample_0 = vk_format_is_int(attachment->format) |
vk_format_is_depth_or_stencil(attachment->format)));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4);

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@ -942,7 +942,7 @@ emit_restore_blit(struct fd_batch *batch,
OUT_REG(ring, A6XX_RB_BLIT_INFO(
.gmem = true, .unk0 = true,
.depth = (buffer == FD_BUFFER_DEPTH),
.integer = util_format_is_pure_integer(psurf->format)));
.sample_0 = util_format_is_pure_integer(psurf->format)));
emit_blit(batch, ring, base, psurf, stencil);
}
@ -1256,7 +1256,7 @@ emit_resolve_blit(struct fd_batch *batch,
}
if (util_format_is_pure_integer(psurf->format))
info |= A6XX_RB_BLIT_INFO_INTEGER;
info |= A6XX_RB_BLIT_INFO_SAMPLE_0;
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, info);