virgl: ARB_enhanced_layouts support

We need to handle the gaps in the streamout bindings on the guest
side and enable if it the host has the rest enabled.

Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>

docs/features.txt

@@ -196,7 +196,7 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
   GL_MAX_VERTEX_ATTRIB_STRIDE                           DONE (all drivers)
   GL_ARB_buffer_storage                                 DONE (freedreno, i965, nv50, llvmpipe, swr)
   GL_ARB_clear_texture                                  DONE (i965, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_enhanced_layouts                               DONE (i965, nv50, llvmpipe, softpipe)
+  GL_ARB_enhanced_layouts                               DONE (i965, nv50, llvmpipe, softpipe, virgl)
   - compile-time constant expressions                   DONE
   - explicit byte offsets for blocks                    DONE
   - forced alignment within blocks                      DONE

src/gallium/drivers/virgl/virgl_encode.c

@@ -880,7 +880,7 @@ int virgl_encoder_set_so_targets(struct virgl_context *ctx,
    virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
    for (i = 0; i < num_targets; i++) {
       struct virgl_so_target *tg = virgl_so_target(targets[i]);
-      virgl_encoder_write_dword(ctx->cbuf, tg->handle);
+      virgl_encoder_write_dword(ctx->cbuf, tg ? tg->handle : 0);
    }
    return 0;
 }

src/gallium/drivers/virgl/virgl_hw.h

@@ -230,6 +230,7 @@ enum virgl_formats {
 #define VIRGL_CAP_TGSI_FBFETCH         (1 << 10)
 #define VIRGL_CAP_SHADER_CLOCK         (1 << 11)
 #define VIRGL_CAP_TEXTURE_BARRIER      (1 << 12)
+#define VIRGL_CAP_TGSI_COMPONENTS      (1 << 13)
 
 /* virgl bind flags - these are compatible with mesa 10.5 gallium.
  * but are fixed, no other should be passed to virgl either.

src/gallium/drivers/virgl/virgl_screen.c

@@ -236,6 +236,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_FBFETCH;
    case PIPE_CAP_TGSI_CLOCK:
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
+   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
    case PIPE_CAP_TEXTURE_GATHER_SM5:
    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
    case PIPE_CAP_FAKE_SW_MSAA:
@@ -272,7 +274,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
-   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_TGSI_MUL_ZERO_WINS:

src/gallium/drivers/virgl/virgl_streamout.c

@@ -72,7 +72,10 @@ static void virgl_set_so_targets(struct pipe_context *ctx,
    struct virgl_context *vctx = virgl_context(ctx);
    int i;
    for (i = 0; i < num_targets; i++) {
-      pipe_resource_reference(&vctx->so_targets[i].base.buffer, targets[i]->buffer);
+      if (targets[i])
+         pipe_resource_reference(&vctx->so_targets[i].base.buffer, targets[i]->buffer);
+      else
+         pipe_resource_reference(&vctx->so_targets[i].base.buffer, NULL);
    }
    for (i = num_targets; i < vctx->num_so_targets; i++)
       pipe_resource_reference(&vctx->so_targets[i].base.buffer, NULL);