radeonsi: align scratch and ring buffer allocations for faster memory access
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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@ -422,7 +422,8 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
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si_aligned_buffer_create(&sctx->screen->b,
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SI_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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scratch_needed, 256);
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scratch_needed,
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sctx->screen->info.pte_fragment_size);
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if (!sctx->compute_scratch_buffer)
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return false;
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@ -977,7 +977,7 @@ static bool si_initialize_prim_discard_cmdbuf(struct si_context *sctx)
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SI_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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sctx->index_ring_size_per_ib * 2,
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2 * 1024 * 1024);
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sctx->screen->info.pte_fragment_size);
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if (!sctx->index_ring)
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return false;
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}
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@ -3487,7 +3487,8 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
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pipe_aligned_buffer_create(sctx->b.screen,
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SI_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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esgs_ring_size, alignment);
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esgs_ring_size,
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sctx->screen->info.pte_fragment_size);
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if (!sctx->esgs_ring)
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return false;
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}
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@ -3498,7 +3499,8 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
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pipe_aligned_buffer_create(sctx->b.screen,
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SI_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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gsvs_ring_size, alignment);
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gsvs_ring_size,
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sctx->screen->info.pte_fragment_size);
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if (!sctx->gsvs_ring)
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return false;
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}
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@ -3735,9 +3737,10 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
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sctx->scratch_buffer =
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si_aligned_buffer_create(&sctx->screen->b,
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SI_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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scratch_needed_size, 256);
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SI_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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scratch_needed_size,
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sctx->screen->info.pte_fragment_size);
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if (!sctx->scratch_buffer)
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return false;
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