i965: Enable ARB_shader_atomic_counter_ops
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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3d2011cb33
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40dd45d0c6
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@ -3793,23 +3793,40 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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switch (instr->intrinsic) {
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case nir_intrinsic_atomic_counter_inc:
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case nir_intrinsic_atomic_counter_dec:
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case nir_intrinsic_atomic_counter_read: {
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case nir_intrinsic_atomic_counter_read:
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case nir_intrinsic_atomic_counter_add:
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case nir_intrinsic_atomic_counter_min:
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case nir_intrinsic_atomic_counter_max:
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case nir_intrinsic_atomic_counter_and:
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case nir_intrinsic_atomic_counter_or:
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case nir_intrinsic_atomic_counter_xor:
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case nir_intrinsic_atomic_counter_exchange:
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case nir_intrinsic_atomic_counter_comp_swap: {
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if (stage == MESA_SHADER_FRAGMENT &&
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instr->intrinsic != nir_intrinsic_atomic_counter_read)
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((struct brw_wm_prog_data *)prog_data)->has_side_effects = true;
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/* Get some metadata from the image intrinsic. */
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const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
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/* Get the arguments of the atomic intrinsic. */
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const fs_reg offset = get_nir_src(instr->src[0]);
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const unsigned surface = (stage_prog_data->binding_table.abo_start +
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instr->const_index[0]);
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const fs_reg src0 = (info->num_srcs >= 2
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? get_nir_src(instr->src[1]) : fs_reg());
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const fs_reg src1 = (info->num_srcs >= 3
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? get_nir_src(instr->src[2]) : fs_reg());
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fs_reg tmp;
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assert(info->num_srcs <= 3);
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/* Emit a surface read or atomic op. */
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if (instr->intrinsic == nir_intrinsic_atomic_counter_read) {
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tmp = emit_untyped_read(bld, brw_imm_ud(surface), offset, 1, 1);
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} else {
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tmp = emit_untyped_atomic(bld, brw_imm_ud(surface), offset, fs_reg(),
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fs_reg(), 1, 1,
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tmp = emit_untyped_atomic(bld, brw_imm_ud(surface), offset, src0,
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src1, 1, 1,
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get_atomic_counter_op(instr->intrinsic));
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}
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@ -612,6 +612,22 @@ get_atomic_counter_op(nir_intrinsic_op op)
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return BRW_AOP_INC;
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case nir_intrinsic_atomic_counter_dec:
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return BRW_AOP_PREDEC;
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case nir_intrinsic_atomic_counter_add:
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return BRW_AOP_ADD;
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case nir_intrinsic_atomic_counter_min:
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return BRW_AOP_UMIN;
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case nir_intrinsic_atomic_counter_max:
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return BRW_AOP_UMAX;
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case nir_intrinsic_atomic_counter_and:
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return BRW_AOP_AND;
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case nir_intrinsic_atomic_counter_or:
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return BRW_AOP_OR;
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case nir_intrinsic_atomic_counter_xor:
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return BRW_AOP_XOR;
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case nir_intrinsic_atomic_counter_exchange:
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return BRW_AOP_MOV;
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case nir_intrinsic_atomic_counter_comp_swap:
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return BRW_AOP_CMPWR;
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default:
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unreachable("Not reachable.");
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}
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@ -739,11 +739,21 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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case nir_intrinsic_atomic_counter_dec: {
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unsigned surf_index = prog_data->base.binding_table.abo_start +
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(unsigned) instr->const_index[0];
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const vec4_builder bld =
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vec4_builder(this).at_end().annotate(current_annotation, base_ir);
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/* Get some metadata from the image intrinsic. */
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const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
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/* Get the arguments of the atomic intrinsic. */
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src_reg offset = get_nir_src(instr->src[0], nir_type_int,
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instr->num_components);
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const src_reg surface = brw_imm_ud(surf_index);
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const vec4_builder bld =
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vec4_builder(this).at_end().annotate(current_annotation, base_ir);
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const src_reg src0 = (info->num_srcs >= 2
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? get_nir_src(instr->src[1]) : src_reg());
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const src_reg src1 = (info->num_srcs >= 3
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? get_nir_src(instr->src[2]) : src_reg());
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src_reg tmp;
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dest = get_nir_dest(instr->dest);
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@ -752,7 +762,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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tmp = emit_untyped_read(bld, surface, offset, 1, 1);
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} else {
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tmp = emit_untyped_atomic(bld, surface, offset,
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src_reg(), src_reg(),
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src0, src1,
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1, 1,
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get_atomic_counter_op(instr->intrinsic));
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}
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@ -346,6 +346,7 @@ intelInitExtensions(struct gl_context *ctx)
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ctx->Extensions.ARB_framebuffer_no_attachments = true;
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ctx->Extensions.ARB_gpu_shader5 = true;
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ctx->Extensions.ARB_shader_atomic_counters = true;
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ctx->Extensions.ARB_shader_atomic_counter_ops = true;
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ctx->Extensions.ARB_shader_clock = true;
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ctx->Extensions.ARB_shader_image_load_store = true;
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ctx->Extensions.ARB_shader_image_size = true;
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