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r600: support tex coords from constants 

Fixes neverball among other things.
This commit is contained in:
Alex Deucher 2009-09-11 11:07:58 -04:00
parent 4108ed7e80
commit 4099bb7614
1 changed files with 17 additions and 45 deletions
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62
src/mesa/drivers/dri/r600/r700_assembler.c
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@ -1149,17 +1149,19 @@ GLboolean tex_dst(r700_AssemblerBase *pAsm)
GLboolean tex_src(r700_AssemblerBase *pAsm)
{
struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
GLboolean bValidTexCoord = GL_FALSE;
switch (pILInst->SrcReg[0].File)
{
case PROGRAM_TEMPORARY:
bValidTexCoord = GL_TRUE;
pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + pAsm->starting_temp_register_number;
pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
break;
case PROGRAM_CONSTANT:
case PROGRAM_LOCAL_PARAM:
case PROGRAM_ENV_PARAM:
case PROGRAM_STATE_VAR:
pAsm->S[0].src.reg = pILInst->SrcReg[0].Index;
pAsm->S[0].src.rtype = SRC_REG_CONSTANT;
break;
case PROGRAM_INPUT:
switch (pILInst->SrcReg[0].Index)
@ -1174,23 +1176,13 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)
case FRAG_ATTRIB_TEX5:
case FRAG_ATTRIB_TEX6:
case FRAG_ATTRIB_TEX7:
bValidTexCoord = GL_TRUE;
pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
pAsm->S[0].src.rtype = SRC_REG_INPUT;
}
break;
}
if(GL_TRUE == bValidTexCoord)
{
setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
}
else
{
radeon_error("Invalid source texcoord for TEX instruction\n");
return GL_FALSE;
}
setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
pAsm->S[0].src.swizzlex = pILInst->SrcReg[0].Swizzle & 0x7;
pAsm->S[0].src.swizzley = (pILInst->SrcReg[0].Swizzle >> 3) & 0x7;
@ -1201,7 +1193,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)
pAsm->S[0].src.negy = (pILInst->SrcReg[0].Negate >> 1) & 0x1;
pAsm->S[0].src.negz = (pILInst->SrcReg[0].Negate >> 2) & 0x1;
pAsm->S[0].src.negw = (pILInst->SrcReg[0].Negate >> 3) & 0x1;
return GL_TRUE;
}
@ -3362,39 +3354,19 @@ GLboolean assemble_STP(r700_AssemblerBase *pAsm)
{
return GL_TRUE;
}
GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
{
GLboolean src_const;
switch (pAsm->pILInst[pAsm->uiCurInst].SrcReg[0].File)
{
case PROGRAM_CONSTANT:
case PROGRAM_LOCAL_PARAM:
case PROGRAM_ENV_PARAM:
case PROGRAM_STATE_VAR:
src_const = GL_TRUE;
case PROGRAM_TEMPORARY:
case PROGRAM_INPUT:
src_const = GL_FALSE;
}
if (GL_TRUE == src_const)
{
radeon_error("TODO: Texture coordinates from a constant register not supported.\n");
return GL_FALSE;
}
switch (pAsm->pILInst[pAsm->uiCurInst].Opcode)
switch (pAsm->pILInst[pAsm->uiCurInst].Opcode)
{
case OPCODE_TEX:
pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
break;
case OPCODE_TXB:
case OPCODE_TXB:
radeon_error("do not support TXB yet\n");
return GL_FALSE;
break;
case OPCODE_TXP:
case OPCODE_TXP:
/* TODO : tex proj version : divid first 3 components by 4th */
pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
break;
@ -3418,13 +3390,13 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
{
return GL_FALSE;
}
if( GL_FALSE == tex_src(pAsm) )
{
return GL_FALSE;
}
if ( GL_FALSE == next_ins(pAsm) )
if ( GL_FALSE == next_ins(pAsm) )
{
return GL_FALSE;
}