freedreno/ir3: ra debug
Some compile time RA debug Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
parent
402c808372
commit
4097ef6ee8
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@ -27,6 +27,8 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdbool.h>
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#include "util/u_debug.h"
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#include "instr-a3xx.h"
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#include "instr-a3xx.h"
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#include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
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#include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
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@ -283,7 +285,7 @@ static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
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{
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{
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if (instr->flags & IR3_INSTR_MARK)
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if (instr->flags & IR3_INSTR_MARK)
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return true; /* already visited */
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return true; /* already visited */
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instr->flags ^= IR3_INSTR_MARK;
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instr->flags |= IR3_INSTR_MARK;
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return false;
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return false;
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}
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}
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@ -405,7 +407,7 @@ static inline bool writes_pred(struct ir3_instruction *instr)
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static inline bool reg_gpr(struct ir3_register *r)
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static inline bool reg_gpr(struct ir3_register *r)
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{
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{
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if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_SSA | IR3_REG_ADDR))
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if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_ADDR))
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return false;
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return false;
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if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
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if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
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return false;
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return false;
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@ -455,7 +457,7 @@ typedef uint8_t regmask_t[2 * MAX_REG / 8];
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static inline unsigned regmask_idx(struct ir3_register *reg)
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static inline unsigned regmask_idx(struct ir3_register *reg)
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{
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{
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unsigned num = reg->num;
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unsigned num = reg->num;
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assert(num < MAX_REG);
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debug_assert(num < MAX_REG);
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if (reg->flags & IR3_REG_HALF)
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if (reg->flags & IR3_REG_HALF)
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num += MAX_REG;
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num += MAX_REG;
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return num;
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return num;
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@ -108,7 +108,7 @@ static void dump_instr_name(struct ir3_dump_ctx *ctx,
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}
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}
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static void dump_reg_name(struct ir3_dump_ctx *ctx,
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static void dump_reg_name(struct ir3_dump_ctx *ctx,
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struct ir3_register *reg)
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struct ir3_register *reg, bool followssa)
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{
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{
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if ((reg->flags & IR3_REG_ABS) && (reg->flags & IR3_REG_NEGATE))
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if ((reg->flags & IR3_REG_ABS) && (reg->flags & IR3_REG_NEGATE))
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fprintf(ctx->f, "(absneg)");
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fprintf(ctx->f, "(absneg)");
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@ -121,9 +121,12 @@ static void dump_reg_name(struct ir3_dump_ctx *ctx,
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fprintf(ctx->f, "imm[%f,%d,0x%x]", reg->fim_val, reg->iim_val, reg->iim_val);
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fprintf(ctx->f, "imm[%f,%d,0x%x]", reg->fim_val, reg->iim_val, reg->iim_val);
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} else if (reg->flags & IR3_REG_SSA) {
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} else if (reg->flags & IR3_REG_SSA) {
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if (ctx->verbose) {
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if (ctx->verbose) {
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fprintf(ctx->f, "_[");
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fprintf(ctx->f, "_");
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dump_instr_name(ctx, reg->instr);
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if (followssa) {
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fprintf(ctx->f, "]");
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fprintf(ctx->f, "[");
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dump_instr_name(ctx, reg->instr);
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fprintf(ctx->f, "]");
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}
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}
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}
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} else {
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} else {
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if (reg->flags & IR3_REG_HALF)
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if (reg->flags & IR3_REG_HALF)
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@ -282,7 +285,7 @@ static void ir3_instr_dump(struct ir3_dump_ctx *ctx,
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if (reg->flags & IR3_REG_SSA)
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if (reg->flags & IR3_REG_SSA)
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fprintf(ctx->f, "<src%u> ", (i - 1));
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fprintf(ctx->f, "<src%u> ", (i - 1));
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dump_reg_name(ctx, reg);
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dump_reg_name(ctx, reg, true);
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}
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}
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fprintf(ctx->f, "}\"];\n");
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fprintf(ctx->f, "}\"];\n");
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@ -406,14 +409,19 @@ ir3_dump_instr_single(struct ir3_instruction *instr)
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for (i = 0; i < instr->regs_count; i++) {
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for (i = 0; i < instr->regs_count; i++) {
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struct ir3_register *reg = instr->regs[i];
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struct ir3_register *reg = instr->regs[i];
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printf(i ? ", " : " ");
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printf(i ? ", " : " ");
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dump_reg_name(&ctx, reg);
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dump_reg_name(&ctx, reg, !!i);
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}
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}
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if (is_meta(instr) && (instr->opc == OPC_META_FO))
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printf(", off=%d", instr->fo.off);
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printf("\n");
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printf("\n");
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}
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}
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void
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void
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ir3_dump_instr_list(struct ir3_instruction *instr)
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ir3_dump_instr_list(struct ir3_instruction *instr)
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{
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{
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struct ir3_block *block = instr->block;
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unsigned n = 0;
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unsigned n = 0;
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while (instr) {
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while (instr) {
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@ -423,4 +431,11 @@ ir3_dump_instr_list(struct ir3_instruction *instr)
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instr = instr->next;
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instr = instr->next;
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}
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}
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printf("%u instructions\n", n);
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printf("%u instructions\n", n);
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for (n = 0; n < block->noutputs; n++) {
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if (!block->outputs[n])
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continue;
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printf("out%d: ", n);
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ir3_dump_instr_single(block->outputs[n]);
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}
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}
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}
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@ -62,6 +62,22 @@ struct ir3_ra_ctx {
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bool error;
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bool error;
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};
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};
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#define ra_debug 0
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#define ra_dump_list(msg, n) do { \
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if (ra_debug) { \
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debug_printf("-- " msg); \
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ir3_dump_instr_list(n); \
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} \
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} while (0)
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#define ra_dump_instr(msg, n) do { \
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if (ra_debug) { \
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debug_printf(">> " msg); \
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ir3_dump_instr_single(n); \
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} \
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} while (0)
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/* sorta ugly way to retrofit half-precision support.. rather than
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/* sorta ugly way to retrofit half-precision support.. rather than
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* passing extra param around, just OR in a high bit. All the low
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* passing extra param around, just OR in a high bit. All the low
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* value arithmetic (ie. +/- offset within a contiguous vec4, etc)
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* value arithmetic (ie. +/- offset within a contiguous vec4, etc)
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@ -92,7 +108,8 @@ static struct ir3_ra_assignment ra_calc(struct ir3_instruction *instr);
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/* check that the register exists, is a GPR and is not special (a0/p0) */
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/* check that the register exists, is a GPR and is not special (a0/p0) */
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static struct ir3_register * reg_check(struct ir3_instruction *instr, unsigned n)
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static struct ir3_register * reg_check(struct ir3_instruction *instr, unsigned n)
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{
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{
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if ((n < instr->regs_count) && reg_gpr(instr->regs[n]))
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if ((n < instr->regs_count) && reg_gpr(instr->regs[n]) &&
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!(instr->regs[n]->flags & IR3_REG_SSA))
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return instr->regs[n];
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return instr->regs[n];
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return NULL;
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return NULL;
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}
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}
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@ -444,9 +461,6 @@ static void ra_assign_reg(struct ir3_visitor *v,
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{
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{
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struct ra_assign_visitor *a = ra_assign_visitor(v);
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struct ra_assign_visitor *a = ra_assign_visitor(v);
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if (is_flow(instr) && (instr->opc == OPC_KILL))
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return;
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reg->flags &= ~IR3_REG_SSA;
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reg->flags &= ~IR3_REG_SSA;
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reg->num = a->num & ~REG_HALF;
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reg->num = a->num & ~REG_HALF;
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@ -582,7 +596,8 @@ static void ir3_instr_ra(struct ir3_ra_ctx *ctx,
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num = regid(REG_A0, 0) | REG_HALF;
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num = regid(REG_A0, 0) | REG_HALF;
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} else {
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} else {
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/* predicate register (p0).. etc */
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/* predicate register (p0).. etc */
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return;
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num = regid(REG_P0, 0);
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debug_assert(dst->num == num);
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}
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}
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ra_assign(ctx, instr, num);
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ra_assign(ctx, instr, num);
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@ -735,6 +750,8 @@ static int block_ra(struct ir3_ra_ctx *ctx, struct ir3_block *block)
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{
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{
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struct ir3_instruction *n;
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struct ir3_instruction *n;
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ra_dump_list("before:\n", block->head);
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if (!block->parent) {
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if (!block->parent) {
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unsigned i, j;
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unsigned i, j;
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int base, off = output_base(ctx);
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int base, off = output_base(ctx);
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@ -765,14 +782,16 @@ static int block_ra(struct ir3_ra_ctx *ctx, struct ir3_block *block)
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}
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}
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}
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}
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ra_dump_list("after:\n", block->head);
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/* then loop over instruction list and assign registers:
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/* then loop over instruction list and assign registers:
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*/
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*/
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n = block->head;
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for (n = block->head; n; n = n->next) {
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while (n) {
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ra_dump_instr("ASSIGN: ", n);
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ir3_instr_ra(ctx, n);
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ir3_instr_ra(ctx, n);
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if (ctx->error)
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if (ctx->error)
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return -1;
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return -1;
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n = n->next;
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ra_dump_list("-------", block->head);
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}
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}
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legalize(ctx, block);
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legalize(ctx, block);
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@ -784,6 +803,7 @@ int ir3_block_ra(struct ir3_block *block, enum shader_t type,
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bool half_precision, bool frag_coord, bool frag_face,
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bool half_precision, bool frag_coord, bool frag_face,
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bool *has_samp, int *max_bary)
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bool *has_samp, int *max_bary)
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{
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{
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struct ir3_instruction *n;
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struct ir3_ra_ctx ctx = {
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struct ir3_ra_ctx ctx = {
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.block = block,
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.block = block,
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.type = type,
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.type = type,
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@ -794,6 +814,13 @@ int ir3_block_ra(struct ir3_block *block, enum shader_t type,
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};
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};
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int ret;
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int ret;
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/* mark dst registers w/ SSA flag so we can see which
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* have been assigned so far:
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*/
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for (n = block->head; n; n = n->next)
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if (n->regs_count > 0)
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n->regs[0]->flags |= IR3_REG_SSA;
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ir3_clear_mark(block->shader);
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ir3_clear_mark(block->shader);
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ret = block_ra(&ctx, block);
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ret = block_ra(&ctx, block);
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*has_samp = ctx.has_samp;
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*has_samp = ctx.has_samp;
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