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ilo: use emit_SURFACE_STATE() for render targets 

Introduce ilo_surface_cso and initialize it in create_surface().  With the
change, we can emit SURFACE_STATE directly from the CSO and remove
emit_surf_SURFACE_STATE().  We do not deal with depth/stencil surfaces yet.
This commit is contained in:
Chia-I Wu 2013-06-03 15:34:13 +08:00
parent 5354dc7428
commit 4006f4ce26
9 changed files with 52 additions and 127 deletions
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1
src/gallium/drivers/ilo/ilo_3d_pipeline.h
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@ -134,7 +134,6 @@ struct ilo_3d_pipeline {
GEN6_EMIT(SCISSOR_RECT);
GEN6_EMIT(BINDING_TABLE_STATE);
GEN6_EMIT(SURFACE_STATE);
GEN6_EMIT(surf_SURFACE_STATE);
GEN6_EMIT(so_SURFACE_STATE);
GEN6_EMIT(SAMPLER_STATE);
GEN6_EMIT(SAMPLER_BORDER_COLOR_STATE);

18
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
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@ -852,11 +852,12 @@ gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline *p,
int i;
for (i = 0; i < ilo->fb.state.nr_cbufs; i++) {
const struct pipe_surface *surface = ilo->fb.state.cbufs[i];
const struct ilo_surface_cso *surface =
(const struct ilo_surface_cso *) ilo->fb.state.cbufs[i];
assert(surface);
assert(surface && surface->is_rt);
surface_state[i] =
p->gen6_surf_SURFACE_STATE(p->dev, surface, p->cp);
p->gen6_SURFACE_STATE(p->dev, &surface->u.rt, true, p->cp);
}
/*
@ -864,14 +865,14 @@ gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline *p,
* brw_update_renderbuffer_surfaces() does. I don't know why.
*/
if (i == 0) {
struct pipe_surface null_surface;
struct ilo_view_surface null_surface;
memset(&null_surface, 0, sizeof(null_surface));
null_surface.width = ilo->fb.state.width;
null_surface.height = ilo->fb.state.height;
ilo_gpe_init_view_surface_null(p->dev,
ilo->fb.state.width, ilo->fb.state.height,
1, 0, &null_surface);
surface_state[i] =
p->gen6_surf_SURFACE_STATE(p->dev, &null_surface, p->cp);
p->gen6_SURFACE_STATE(p->dev, &null_surface, true, p->cp);
i++;
}
@ -1642,7 +1643,6 @@ ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline *p)
GEN6_USE(p, SCISSOR_RECT, gen6);
GEN6_USE(p, BINDING_TABLE_STATE, gen6);
GEN6_USE(p, SURFACE_STATE, gen6);
GEN6_USE(p, surf_SURFACE_STATE, gen6);
GEN6_USE(p, so_SURFACE_STATE, gen6);
GEN6_USE(p, SAMPLER_STATE, gen6);
GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen6);

1
src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
View File

@ -829,7 +829,6 @@ ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p)
GEN6_USE(p, SCISSOR_RECT, gen7);
GEN6_USE(p, BINDING_TABLE_STATE, gen7);
GEN6_USE(p, SURFACE_STATE, gen7);
GEN6_USE(p, surf_SURFACE_STATE, gen7);
GEN6_USE(p, SAMPLER_STATE, gen7);
GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen7);
GEN6_USE(p, push_constant_buffer, gen7);

9
src/gallium/drivers/ilo/ilo_gpe.h
View File

@ -194,6 +194,15 @@ struct ilo_resource_state {
unsigned count;
};
struct ilo_surface_cso {
struct pipe_surface base;
bool is_rt;
union {
struct ilo_view_surface rt;
} u;
};
struct ilo_fb_state {
struct pipe_framebuffer_state state;

31
src/gallium/drivers/ilo/ilo_gpe_gen6.c
View File

@ -4186,36 +4186,6 @@ gen6_emit_SURFACE_STATE(const struct ilo_dev_info *dev,
return state_offset;
}
static uint32_t
gen6_emit_surf_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
struct ilo_cp *cp)
{
struct ilo_view_surface surf;
ILO_GPE_VALID_GEN(dev, 6, 6);
if (surface && surface->texture) {
struct ilo_texture *tex = ilo_texture(surface->texture);
/*
* classic i965 sets render_cache_rw for constant buffers and sol
* surfaces but not render buffers. Why?
*/
ilo_gpe_init_view_surface_for_texture_gen6(dev, tex, surface->format,
surface->u.tex.level, 1,
surface->u.tex.first_layer,
surface->u.tex.last_layer - surface->u.tex.first_layer + 1,
true, true, &surf);
}
else {
ilo_gpe_init_view_surface_null_gen6(dev,
surface->width, surface->height, 1, 0, &surf);
}
return gen6_emit_SURFACE_STATE(dev, &surf, true, cp);
}
static uint32_t
gen6_emit_so_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct pipe_stream_output_target *so,
@ -4942,7 +4912,6 @@ static const struct ilo_gpe_gen6 gen6_gpe = {
GEN6_SET(SCISSOR_RECT),
GEN6_SET(BINDING_TABLE_STATE),
GEN6_SET(SURFACE_STATE),
GEN6_SET(surf_SURFACE_STATE),
GEN6_SET(so_SURFACE_STATE),
GEN6_SET(SAMPLER_STATE),
GEN6_SET(SAMPLER_BORDER_COLOR_STATE),

6
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View File

@ -428,11 +428,6 @@ typedef uint32_t
bool for_render,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_surf_SURFACE_STATE)(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
struct ilo_cp *cp);
typedef uint32_t
(*ilo_gpe_gen6_so_SURFACE_STATE)(const struct ilo_dev_info *dev,
const struct pipe_stream_output_target *so,
@ -525,7 +520,6 @@ struct ilo_gpe_gen6 {
GEN6_EMIT(SCISSOR_RECT);
GEN6_EMIT(BINDING_TABLE_STATE);
GEN6_EMIT(SURFACE_STATE);
GEN6_EMIT(surf_SURFACE_STATE);
GEN6_EMIT(so_SURFACE_STATE);
GEN6_EMIT(SAMPLER_STATE);
GEN6_EMIT(SAMPLER_BORDER_COLOR_STATE);

66
src/gallium/drivers/ilo/ilo_gpe_gen7.c
View File

@ -1652,71 +1652,6 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
surf->bo = tex->bo;
}
static uint32_t
gen7_emit_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct ilo_view_surface *surf,
bool for_render, struct ilo_cp *cp)
{
const int state_align = 32 / 4;
const int state_len = 8;
uint32_t state_offset;
uint32_t read_domains, write_domain;
ILO_GPE_VALID_GEN(dev, 7, 7);
if (for_render) {
read_domains = INTEL_DOMAIN_RENDER;
write_domain = INTEL_DOMAIN_RENDER;
}
else {
read_domains = INTEL_DOMAIN_SAMPLER;
write_domain = 0;
}
ilo_cp_steal(cp, "SURFACE_STATE", state_len, state_align, &state_offset);
ilo_cp_write(cp, surf->payload[0]);
ilo_cp_write_bo(cp, surf->payload[1], surf->bo, read_domains, write_domain);
ilo_cp_write(cp, surf->payload[2]);
ilo_cp_write(cp, surf->payload[3]);
ilo_cp_write(cp, surf->payload[4]);
ilo_cp_write(cp, surf->payload[5]);
ilo_cp_write(cp, surf->payload[6]);
ilo_cp_write(cp, surf->payload[7]);
ilo_cp_end(cp);
return state_offset;
}
static uint32_t
gen7_emit_surf_SURFACE_STATE(const struct ilo_dev_info *dev,
const struct pipe_surface *surface,
struct ilo_cp *cp)
{
struct ilo_view_surface surf;
ILO_GPE_VALID_GEN(dev, 7, 7);
if (surface && surface->texture) {
struct ilo_texture *tex = ilo_texture(surface->texture);
/*
* classic i965 sets render_cache_rw for constant buffers and sol
* surfaces but not render buffers. Why?
*/
ilo_gpe_init_view_surface_for_texture_gen7(dev, tex, surface->format,
surface->u.tex.level, 1,
surface->u.tex.first_layer,
surface->u.tex.last_layer - surface->u.tex.first_layer + 1,
true, true, &surf);
}
else {
ilo_gpe_init_view_surface_null_gen7(dev,
surface->width, surface->height, 1, 0, &surf);
}
return gen7_emit_SURFACE_STATE(dev, &surf, true, cp);
}
static int
gen7_estimate_command_size(const struct ilo_dev_info *dev,
enum ilo_gpe_gen7_command cmd,
@ -1942,7 +1877,6 @@ gen7_init(struct ilo_gpe_gen7 *gen7)
GEN7_USE(gen7, SCISSOR_RECT, gen6);
GEN7_USE(gen7, BINDING_TABLE_STATE, gen6);
GEN7_USE(gen7, SURFACE_STATE, gen6);
GEN7_SET(gen7, surf_SURFACE_STATE);
GEN7_USE(gen7, SAMPLER_STATE, gen6);
GEN7_USE(gen7, SAMPLER_BORDER_COLOR_STATE, gen6);
GEN7_USE(gen7, push_constant_buffer, gen6);

2
src/gallium/drivers/ilo/ilo_gpe_gen7.h
View File

@ -386,7 +386,6 @@ typedef ilo_gpe_gen6_DEPTH_STENCIL_STATE ilo_gpe_gen7_DEPTH_STENCIL_STATE;
typedef ilo_gpe_gen6_SCISSOR_RECT ilo_gpe_gen7_SCISSOR_RECT;
typedef ilo_gpe_gen6_BINDING_TABLE_STATE ilo_gpe_gen7_BINDING_TABLE_STATE;
typedef ilo_gpe_gen6_SURFACE_STATE ilo_gpe_gen7_SURFACE_STATE;
typedef ilo_gpe_gen6_surf_SURFACE_STATE ilo_gpe_gen7_surf_SURFACE_STATE;
typedef ilo_gpe_gen6_SAMPLER_STATE ilo_gpe_gen7_SAMPLER_STATE;
typedef ilo_gpe_gen6_SAMPLER_BORDER_COLOR_STATE ilo_gpe_gen7_SAMPLER_BORDER_COLOR_STATE;
typedef ilo_gpe_gen6_push_constant_buffer ilo_gpe_gen7_push_constant_buffer;
@ -483,7 +482,6 @@ struct ilo_gpe_gen7 {
GEN7_EMIT(SCISSOR_RECT);
GEN7_EMIT(BINDING_TABLE_STATE);
GEN7_EMIT(SURFACE_STATE);
GEN7_EMIT(surf_SURFACE_STATE);
GEN7_EMIT(SAMPLER_STATE);
GEN7_EMIT(SAMPLER_BORDER_COLOR_STATE);
GEN7_EMIT(push_constant_buffer);

45
src/gallium/drivers/ilo/ilo_state.c
View File

@ -894,21 +894,44 @@ ilo_create_surface(struct pipe_context *pipe,
struct pipe_resource *res,
const struct pipe_surface *templ)
{
struct pipe_surface *surface;
struct ilo_context *ilo = ilo_context(pipe);
struct ilo_surface_cso *surf;
surface = MALLOC_STRUCT(pipe_surface);
assert(surface);
surf = MALLOC_STRUCT(ilo_surface_cso);
assert(surf);
*surface = *templ;
pipe_reference_init(&surface->reference, 1);
surface->texture = NULL;
pipe_resource_reference(&surface->texture, res);
surf->base = *templ;
pipe_reference_init(&surf->base.reference, 1);
surf->base.texture = NULL;
pipe_resource_reference(&surf->base.texture, res);
surface->context = pipe;
surface->width = u_minify(res->width0, surface->u.tex.level);
surface->height = u_minify(res->height0, surface->u.tex.level);
surf->base.context = pipe;
surf->base.width = u_minify(res->width0, templ->u.tex.level);
surf->base.height = u_minify(res->height0, templ->u.tex.level);
return surface;
surf->is_rt = !util_format_is_depth_or_stencil(templ->format);
if (surf->is_rt) {
/* relax this? */
assert(res->target != PIPE_BUFFER);
/*
* classic i965 sets render_cache_rw for constant buffers and sol
* surfaces but not render buffers. Why?
*/
ilo_gpe_init_view_surface_for_texture(ilo->dev, ilo_texture(res),
templ->format, templ->u.tex.level, 1,
templ->u.tex.first_layer,
templ->u.tex.last_layer - templ->u.tex.first_layer + 1,
true, true, &surf->u.rt);
}
else {
assert(res->target != PIPE_BUFFER);
/* will construct dynamically */
}
return &surf->base;
}
static void