i965/fs: Add unit tests for cmod propagation pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner
parent
19f9cb72c8
commit
3fb5b2bc47
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@ -52,6 +52,7 @@ TEST_LIBS = \
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../common/libdri_test_stubs.la
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TESTS = \
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test_fs_cmod_propagation \
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test_eu_compact \
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test_vf_float_conversions \
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test_vec4_copy_propagation \
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@ -59,6 +60,12 @@ TESTS = \
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check_PROGRAMS = $(TESTS)
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test_fs_cmod_propagation_SOURCES = \
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test_fs_cmod_propagation.cpp
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test_fs_cmod_propagation_LDADD = \
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$(TEST_LIBS) \
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$(top_builddir)/src/gtest/libgtest.la
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test_vf_float_conversions_SOURCES = \
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test_vf_float_conversions.cpp
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test_vf_float_conversions_LDADD = \
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@ -0,0 +1,311 @@
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <gtest/gtest.h>
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#include "program/program.h"
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class cmod_propagation_test : public ::testing::Test {
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virtual void SetUp();
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public:
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struct brw_context *brw;
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struct gl_context *ctx;
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struct brw_wm_prog_data *prog_data;
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struct gl_shader_program *shader_prog;
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struct brw_fragment_program *fp;
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fs_visitor *v;
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};
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class cmod_propagation_fs_visitor : public fs_visitor
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{
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public:
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cmod_propagation_fs_visitor(struct brw_context *brw,
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struct brw_wm_prog_data *prog_data,
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struct gl_shader_program *shader_prog)
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: fs_visitor(brw, NULL, NULL, prog_data, shader_prog, NULL, 8) {}
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};
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void cmod_propagation_test::SetUp()
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{
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brw = (struct brw_context *)calloc(1, sizeof(*brw));
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ctx = &brw->ctx;
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fp = ralloc(NULL, struct brw_fragment_program);
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prog_data = ralloc(NULL, struct brw_wm_prog_data);
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shader_prog = ralloc(NULL, struct gl_shader_program);
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v = new cmod_propagation_fs_visitor(brw, prog_data, shader_prog);
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_mesa_init_fragment_program(ctx, &fp->program, GL_FRAGMENT_SHADER, 0);
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brw->gen = 4;
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}
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static fs_inst *
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instruction(bblock_t *block, int num)
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{
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fs_inst *inst = (fs_inst *)block->start();
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for (int i = 0; i < num; i++) {
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inst = (fs_inst *)inst->next;
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}
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return inst;
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}
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static bool
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cmod_propagation(fs_visitor *v)
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{
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const bool print = false;
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if (print) {
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fprintf(stderr, "= Before =\n");
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v->cfg->dump(v);
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}
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bool ret = v->opt_cmod_propagation();
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if (print) {
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fprintf(stderr, "\n= After =\n");
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v->cfg->dump(v);
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}
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return ret;
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}
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TEST_F(cmod_propagation_test, basic)
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{
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fs_reg dest = v->vgrf(glsl_type::float_type);
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fs_reg src0 = v->vgrf(glsl_type::float_type);
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fs_reg src1 = v->vgrf(glsl_type::float_type);
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fs_reg zero(0.0f);
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v->emit(BRW_OPCODE_ADD, dest, src0, src1);
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v->emit(BRW_OPCODE_CMP, v->reg_null_f, dest, zero)
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->conditional_mod = BRW_CONDITIONAL_GE;
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/* = Before =
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*
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* 0: add(8) dest src0 src1
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* 1: cmp.ge.f0(8) null dest 0.0f
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*
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* = After =
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* 0: add.ge.f0(8) dest src0 src1
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_TRUE(cmod_propagation(v));
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(0, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
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}
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TEST_F(cmod_propagation_test, cmp_nonzero)
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{
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fs_reg dest = v->vgrf(glsl_type::float_type);
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fs_reg src0 = v->vgrf(glsl_type::float_type);
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fs_reg src1 = v->vgrf(glsl_type::float_type);
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fs_reg nonzero(1.0f);
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v->emit(BRW_OPCODE_ADD, dest, src0, src1);
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v->emit(BRW_OPCODE_CMP, v->reg_null_f, dest, nonzero)
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->conditional_mod = BRW_CONDITIONAL_GE;
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/* = Before =
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*
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* 0: add(8) dest src0 src1
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* 1: cmp.ge.f0(8) null dest 1.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
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}
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TEST_F(cmod_propagation_test, non_cmod_instruction)
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{
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fs_reg dest = v->vgrf(glsl_type::uint_type);
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fs_reg src0 = v->vgrf(glsl_type::uint_type);
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fs_reg zero(0u);
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v->emit(BRW_OPCODE_FBL, dest, src0);
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v->emit(BRW_OPCODE_CMP, v->reg_null_ud, dest, zero)
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->conditional_mod = BRW_CONDITIONAL_GE;
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/* = Before =
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*
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* 0: fbl(8) dest src0
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* 1: cmp.ge.f0(8) null dest 0u
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(1, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_FBL, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
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}
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TEST_F(cmod_propagation_test, intervening_flag_write)
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{
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fs_reg dest = v->vgrf(glsl_type::float_type);
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fs_reg src0 = v->vgrf(glsl_type::float_type);
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fs_reg src1 = v->vgrf(glsl_type::float_type);
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fs_reg src2 = v->vgrf(glsl_type::float_type);
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fs_reg zero(0.0f);
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v->emit(BRW_OPCODE_ADD, dest, src0, src1);
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v->emit(BRW_OPCODE_CMP, v->reg_null_f, src2, zero)
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->conditional_mod = BRW_CONDITIONAL_GE;
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v->emit(BRW_OPCODE_CMP, v->reg_null_f, dest, zero)
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->conditional_mod = BRW_CONDITIONAL_GE;
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/* = Before =
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*
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* 0: add(8) dest src0 src1
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* 1: cmp.ge.f0(8) null src2 0.0f
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* 2: cmp.ge.f0(8) null dest 0.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
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}
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TEST_F(cmod_propagation_test, intervening_flag_read)
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{
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fs_reg dest0 = v->vgrf(glsl_type::float_type);
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fs_reg dest1 = v->vgrf(glsl_type::float_type);
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fs_reg src0 = v->vgrf(glsl_type::float_type);
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fs_reg src1 = v->vgrf(glsl_type::float_type);
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fs_reg src2 = v->vgrf(glsl_type::float_type);
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fs_reg zero(0.0f);
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v->emit(BRW_OPCODE_ADD, dest0, src0, src1);
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v->emit(BRW_OPCODE_SEL, dest1, src2, zero)
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->predicate = BRW_PREDICATE_NORMAL;
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v->emit(BRW_OPCODE_CMP, v->reg_null_f, dest0, zero)
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->conditional_mod = BRW_CONDITIONAL_GE;
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/* = Before =
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*
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* 0: add(8) dest0 src0 src1
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* 1: (+f0) sel(8) dest1 src2 0.0f
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* 2: cmp.ge.f0(8) null dest0 0.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
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}
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TEST_F(cmod_propagation_test, intervening_dest_write)
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{
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fs_reg dest = v->vgrf(glsl_type::vec4_type);
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fs_reg src0 = v->vgrf(glsl_type::float_type);
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fs_reg src1 = v->vgrf(glsl_type::float_type);
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fs_reg src2 = v->vgrf(glsl_type::vec2_type);
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fs_reg zero(0.0f);
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v->emit(BRW_OPCODE_ADD, offset(dest, 2), src0, src1);
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v->emit(SHADER_OPCODE_TEX, dest, src2)
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->regs_written = 4;
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v->emit(BRW_OPCODE_CMP, v->reg_null_f, offset(dest, 2), zero)
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->conditional_mod = BRW_CONDITIONAL_GE;
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/* = Before =
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*
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* 0: add(8) dest+2 src0 src1
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* 1: tex(8) rlen 4 dest+0 src2
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* 2: cmp.ge.f0(8) null dest+2 0.0f
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*
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* = After =
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* (no changes)
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*/
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_FALSE(cmod_propagation(v));
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EXPECT_EQ(0, block0->start_ip);
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EXPECT_EQ(2, block0->end_ip);
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EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
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EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod);
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EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode);
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EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
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}
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