radeonsi: enable signed vertex buffer offsets
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24d6318d24
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3f58988b81
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@ -995,7 +995,6 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
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unsigned i, count;
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unsigned desc_list_byte_size;
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unsigned first_vb_use_mask;
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uint64_t va;
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uint32_t *ptr;
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if (!sctx->vertex_buffers_dirty || !velems)
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@ -1035,7 +1034,6 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
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for (i = 0; i < count; i++) {
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struct pipe_vertex_buffer *vb;
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struct r600_resource *rbuffer;
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unsigned offset;
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unsigned vbo_index = velems->vertex_buffer_index[i];
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uint32_t *desc = &ptr[i*4];
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@ -1046,23 +1044,22 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
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continue;
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}
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offset = vb->buffer_offset + velems->src_offset[i];
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va = rbuffer->gpu_address + offset;
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int offset = (int)vb->buffer_offset + (int)velems->src_offset[i];
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int64_t va = (int64_t)rbuffer->gpu_address + offset;
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assert(va > 0);
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int64_t num_records = (int64_t)rbuffer->b.b.width0 - offset;
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if (sctx->b.chip_class != VI && vb->stride) {
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/* Round up by rounding down and adding 1 */
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num_records = (num_records - velems->format_size[i]) /
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vb->stride + 1;
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}
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assert(num_records >= 0 && num_records <= UINT_MAX);
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/* Fill in T# buffer resource description */
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(vb->stride);
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if (sctx->b.chip_class != VI && vb->stride) {
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/* Round up by rounding down and adding 1 */
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desc[2] = (vb->buffer.resource->width0 - offset -
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velems->format_size[i]) /
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vb->stride + 1;
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} else {
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desc[2] = vb->buffer.resource->width0 - offset;
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}
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desc[2] = num_records;
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desc[3] = velems->rsrc_word3[i];
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if (first_vb_use_mask & (1 << i)) {
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@ -507,6 +507,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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return 1;
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case PIPE_CAP_TGSI_VOTE:
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@ -590,7 +591,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_POST_DEPTH_COVERAGE:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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return 0;
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case PIPE_CAP_NATIVE_FENCE_FD:
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