i965/nir: Replace fs_reg(GRF, virtual_grf_alloc(...)) with vgrf(...).
brw_fs_nir.cpp creates almost all of its registers via: fs_reg reg = fs_reg(GRF, virtual_grf_alloc(num_components)); When we add SIMD16 support, we'll need to set reg->width = 16 and double the VGRF size...on pretty much every VGRF it allocates. This patch replaces that pattern with a new "vgrf" helper method: fs_reg reg = vgrf(num_components); The new function correctly takes reg_width into account. For now, reg_width is always 1, so this should have no functional change. v2: Just make vgrf() account for reg_width right away, rather than changing the behavior in the next patch. v3: Replace one last virtual_grf_alloc I missed. It's used in code that only runs for dispatch_width == 8, so it doesn't matter, but consistency is nice. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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@ -1040,6 +1040,14 @@ fs_visitor::vgrf(const glsl_type *const type)
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brw_type_for_base_type(type), dispatch_width);
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}
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fs_reg
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fs_visitor::vgrf(int num_components)
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{
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int reg_width = dispatch_width / 8;
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return fs_reg(GRF, virtual_grf_alloc(num_components * reg_width),
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BRW_REGISTER_TYPE_F, dispatch_width);
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}
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/** Fixed HW reg constructor. */
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fs_reg::fs_reg(enum register_file file, int reg)
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{
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@ -323,6 +323,7 @@ public:
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fs_reg *variable_storage(ir_variable *var);
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int virtual_grf_alloc(int size);
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fs_reg vgrf(const glsl_type *const type);
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fs_reg vgrf(int num_components);
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void import_uniforms(fs_visitor *v);
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void setup_uniform_clipplane_values();
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void compute_clip_distance();
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@ -95,12 +95,12 @@ fs_visitor::emit_nir_code()
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*/
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if (nir->num_inputs > 0) {
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nir_inputs = fs_reg(GRF, virtual_grf_alloc(nir->num_inputs));
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nir_inputs = vgrf(nir->num_inputs);
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nir_setup_inputs(nir);
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}
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if (nir->num_outputs > 0) {
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nir_outputs = fs_reg(GRF, virtual_grf_alloc(nir->num_outputs));
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nir_outputs = vgrf(nir->num_outputs);
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nir_setup_outputs(nir);
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}
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@ -116,7 +116,7 @@ fs_visitor::emit_nir_code()
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unsigned array_elems =
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reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
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unsigned size = array_elems * reg->num_components;
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nir_globals[reg->index] = fs_reg(GRF, virtual_grf_alloc(size));
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nir_globals[reg->index] = vgrf(size);
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}
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/* get the main function and emit it */
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@ -356,7 +356,7 @@ fs_visitor::nir_emit_impl(nir_function_impl *impl)
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unsigned array_elems =
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reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
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unsigned size = array_elems * reg->num_components;
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nir_locals[reg->index] = fs_reg(GRF, virtual_grf_alloc(size));
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nir_locals[reg->index] = vgrf(size);
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}
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nir_emit_cf_list(&impl->body);
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@ -730,7 +730,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
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case nir_op_ball_fequal4:
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case nir_op_ball_iequal4: {
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unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
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fs_reg temp = fs_reg(GRF, virtual_grf_alloc(num_components));
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fs_reg temp = vgrf(num_components);
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emit_percomp(CMP(temp, op[0], op[1], BRW_CONDITIONAL_Z),
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(1 << num_components) - 1);
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emit_reduction(BRW_OPCODE_AND, result, temp, num_components);
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@ -744,7 +744,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
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case nir_op_bany_fnequal4:
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case nir_op_bany_inequal4: {
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unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
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fs_reg temp = fs_reg(GRF, virtual_grf_alloc(num_components));
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fs_reg temp = vgrf(num_components);
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temp.type = BRW_REGISTER_TYPE_UD;
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emit_percomp(CMP(temp, op[0], op[1], BRW_CONDITIONAL_NZ),
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(1 << num_components) - 1);
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@ -769,7 +769,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
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case nir_op_fdot3:
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case nir_op_fdot4: {
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unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
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fs_reg temp = fs_reg(GRF, virtual_grf_alloc(num_components));
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fs_reg temp = vgrf(num_components);
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emit_percomp(MUL(temp, op[0], op[1]), (1 << num_components) - 1);
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emit_reduction(BRW_OPCODE_ADD, result, temp, num_components);
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if (instr->dest.saturate) {
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@ -1038,8 +1038,8 @@ fs_visitor::get_nir_src(nir_src src)
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if (src.is_ssa) {
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assert(src.ssa->parent_instr->type == nir_instr_type_load_const);
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nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
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fs_reg reg(GRF, virtual_grf_alloc(src.ssa->num_components),
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BRW_REGISTER_TYPE_D);
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fs_reg reg = vgrf(src.ssa->num_components);
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reg.type = BRW_REGISTER_TYPE_D;
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for (unsigned i = 0; i < src.ssa->num_components; ++i)
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emit(MOV(offset(reg, i), fs_reg(load->value.i[i])));
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@ -1091,7 +1091,8 @@ fs_visitor::get_nir_alu_src(nir_alu_instr *instr, unsigned src)
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if (needs_swizzle) {
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/* resolve the swizzle through MOV's */
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fs_reg new_reg = fs_reg(GRF, virtual_grf_alloc(num_components), reg.type);
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fs_reg new_reg = vgrf(num_components);
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new_reg.type = reg.type;
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for (unsigned i = 0; i < 4; i++) {
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if (!nir_alu_instr_channel_used(instr, src, i))
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@ -1244,7 +1245,7 @@ fs_visitor::emit_reduction(enum opcode op, fs_reg dest, fs_reg src,
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return;
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}
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fs_reg temp1 = fs_reg(GRF, virtual_grf_alloc(1));
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fs_reg temp1 = vgrf(1);
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temp1.type = src.type;
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emit(op, temp1, src0, src1);
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@ -1260,7 +1261,7 @@ fs_visitor::emit_reduction(enum opcode op, fs_reg dest, fs_reg src,
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fs_reg src3 = src;
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src3.reg_offset += 3;
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fs_reg temp2 = fs_reg(GRF, virtual_grf_alloc(1));
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fs_reg temp2 = vgrf(1);
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temp2.type = src.type;
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emit(op, temp2, src2, src3);
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@ -1487,7 +1488,7 @@ fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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*/
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no16("interpolate_at_* not yet supported in SIMD16 mode.");
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fs_reg dst_x(GRF, virtual_grf_alloc(2), BRW_REGISTER_TYPE_F);
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fs_reg dst_x = vgrf(2);
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fs_reg dst_y = offset(dst_x, 1);
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/* For most messages, we need one reg of ignored data; the hardware
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