intel/tools: Simplify register type handling
Produce a brw_reg_type rather than a whole brw_reg and rename a few non-terminals. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
This commit is contained in:
Matt Turner
parent
2851c218e2
commit
3e1602cc4f
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@ -321,6 +321,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
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int integer;
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unsigned long long int llint;
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struct brw_reg reg;
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enum brw_reg_type reg_type;
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struct brw_codegen *program;
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struct predicate predicate;
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struct condition condition;
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@ -469,7 +470,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
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%type <reg> writemask
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/* dst operand */
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%type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
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%type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
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%type <integer> dstregion
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%type <integer> saturate relativelocation rellocation
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@ -477,8 +478,8 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
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/* src operand */
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%type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
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%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
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%type <reg> srcimmtype indirectgenreg indirectregion
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%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
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%type <reg> indirectgenreg indirectregion
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%type <reg> immreg src reg32 payload directgenreg_list addrparam region
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%type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
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@ -487,6 +488,9 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
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%type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
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%type <integer> subregnum
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/* register types */
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%type <reg_type> reg_type imm_type
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/* immediate values */
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%type <llint> immval
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@ -1418,7 +1422,7 @@ dst:
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;
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dstoperand:
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dstreg dstregion writemask dsttype
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dstreg dstregion writemask reg_type
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{
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$$ = $1;
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@ -1429,27 +1433,27 @@ dstoperand:
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} else {
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$$.hstride = $2;
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}
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$$.type = $4.type;
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$$.type = $4;
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$$.writemask = $3.writemask;
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$$.swizzle = BRW_SWIZZLE_NOOP;
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$$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
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$$.subnr = $$.subnr * brw_reg_type_to_size($4);
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}
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;
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dstoperandex:
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dstoperandex_typed dstregion writemask dsttype
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dstoperandex_typed dstregion writemask reg_type
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{
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$$ = $1;
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$$.hstride = $2;
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$$.type = $4.type;
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$$.type = $4;
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$$.writemask = $3.writemask;
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$$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
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$$.subnr = $$.subnr * brw_reg_type_to_size($4);
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}
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/* BSpec says "When the conditional modifier is present, updates
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* to the selected flag register also occur. In this case, the
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* register region fields of the ‘null’ operand are valid."
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*/
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| nullreg dstregion writemask dsttype
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| nullreg dstregion writemask reg_type
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{
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$$ = $1;
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if ($2 == -1) {
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@ -1460,7 +1464,7 @@ dstoperandex:
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$$.hstride = $2;
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}
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$$.writemask = $3.writemask;
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$$.type = $4.type;
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$$.type = $4;
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}
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| threadcontrolreg
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{
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@ -1512,11 +1516,11 @@ srcaccimm:
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;
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immreg:
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immval srcimmtype
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immval imm_type
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{
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uint32_t u32;
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uint64_t u64;
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switch ($2.type) {
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switch ($2) {
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case BRW_REGISTER_TYPE_UD:
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u32 = $1;
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$$ = brw_imm_ud(u32);
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@ -1561,15 +1565,15 @@ immreg:
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break;
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default:
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error(&@2, "Unknown immediate type %s\n",
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brw_reg_type_to_letters($2.type));
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brw_reg_type_to_letters($2));
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}
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}
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;
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reg32:
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directgenreg region srctype
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directgenreg region reg_type
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{
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$$ = set_direct_src_operand(&$1, $3.type);
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$$ = set_direct_src_operand(&$1, $3);
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$$ = stride($$, $2.vstride, $2.width, $2.hstride);
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}
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;
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@ -1596,9 +1600,9 @@ srcimm:
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directsrcaccoperand:
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directsrcoperand
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| accreg region srctype
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| accreg region reg_type
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{
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$$ = set_direct_src_operand(&$1, $3.type);
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$$ = set_direct_src_operand(&$1, $3);
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$$.vstride = $2.vstride;
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$$.width = $2.width;
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$$.hstride = $2.hstride;
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@ -1606,23 +1610,23 @@ directsrcaccoperand:
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;
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srcarcoperandex:
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srcarcoperandex_typed region srctype
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srcarcoperandex_typed region reg_type
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{
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$$ = brw_reg($1.file,
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$1.nr,
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$1.subnr,
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0,
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0,
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$3.type,
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$3,
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$2.vstride,
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$2.width,
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$2.hstride,
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BRW_SWIZZLE_NOOP,
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WRITEMASK_XYZW);
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}
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| nullreg region srctype
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| nullreg region reg_type
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{
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$$ = set_direct_src_operand(&$1, $3.type);
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$$ = set_direct_src_operand(&$1, $3);
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$$.vstride = $2.vstride;
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$$.width = $2.width;
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$$.hstride = $2.hstride;
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@ -1643,14 +1647,14 @@ srcarcoperandex_typed:
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;
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indirectsrcoperand:
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negate abs indirectgenreg indirectregion swizzle srctype
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negate abs indirectgenreg indirectregion swizzle reg_type
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{
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$$ = brw_reg($3.file,
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0,
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$3.subnr,
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$1, // negate
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$2, // abs
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$6.type,
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$6,
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$4.vstride,
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$4.width,
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$4.hstride,
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@ -1672,14 +1676,14 @@ directgenreg_list:
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;
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directsrcoperand:
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negate abs directgenreg_list region swizzle srctype
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negate abs directgenreg_list region swizzle reg_type
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{
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$$ = brw_reg($3.file,
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$3.nr,
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$3.subnr,
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$1,
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$2,
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$6.type,
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$6,
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$4.vstride,
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$4.width,
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$4.hstride,
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@ -2012,30 +2016,26 @@ region_wh:
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}
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;
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srctype:
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TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); }
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| TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
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| TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); }
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| TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
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| TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); }
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| TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
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| TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); }
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| TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
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| TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
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| TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
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| TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
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| TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
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reg_type:
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TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
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| TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
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| TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
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| TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
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| TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
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| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
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| TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
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| TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
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| TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
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| TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
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| TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
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| TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
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;
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srcimmtype:
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srctype { $$ = $1; }
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| TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); }
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| TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
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| TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
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;
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dsttype:
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srctype { $$ = $1; }
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imm_type:
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reg_type { $$ = $1; }
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| TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
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| TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
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| TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
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;
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writemask:
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