From 3de072aaecf3a99699f539d33c5f374070334078 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Fri, 5 Nov 2021 22:00:33 +0100 Subject: [PATCH] radeonsi/sqtt: fix shader stage values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit shader_stages_mask and others expect MESA_SHADER_* based values, not PIPE_SHADER_*... Without this the fragment shader wouldn't appear in the "Pipelines" pane of RGP. Fixes: c276bde34ae ("radeonsi/sqtt: export shader code to RGP") Reviewed-by: Marek Olšák Part-of: --- src/gallium/drivers/radeonsi/si_sqtt.c | 29 +++++++++++++------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c index e92259b4638..44a77dc3a40 100644 --- a/src/gallium/drivers/radeonsi/si_sqtt.c +++ b/src/gallium/drivers/radeonsi/si_sqtt.c @@ -31,6 +31,7 @@ #include "ac_rgp.h" #include "ac_sqtt.h" #include "util/u_memory.h" +#include "tgsi/tgsi_from_mesa.h" static void si_emit_spi_config_cntl(struct si_context* sctx, @@ -957,7 +958,6 @@ si_sqtt_pipe_to_rgp_shader_stage(union si_shader_key* key, enum pipe_shader_type } } - static bool si_sqtt_add_code_object(struct si_context* sctx, uint64_t pipeline_hash, @@ -1002,20 +1002,21 @@ si_sqtt_add_code_object(struct si_context* sctx, memcpy(code, shader->binary.uploaded_code, shader->binary.uploaded_code_size); uint64_t va = shader->bo->gpu_address; - record->shader_data[i].hash[0] = _mesa_hash_data(code, shader->binary.uploaded_code_size); - record->shader_data[i].hash[1] = record->shader_data[i].hash[0]; - record->shader_data[i].code_size = shader->binary.uploaded_code_size; - record->shader_data[i].code = code; - record->shader_data[i].vgpr_count = shader->config.num_vgprs; - record->shader_data[i].sgpr_count = shader->config.num_sgprs; - record->shader_data[i].base_address = va & 0xffffffffffff; - record->shader_data[i].elf_symbol_offset = 0; - record->shader_data[i].hw_stage = hw_stage; - record->shader_data[i].is_combined = false; - record->shader_data[i].scratch_memory_size = shader->config.scratch_bytes_per_wave; - record->shader_data[i].wavefront_size = si_get_shader_wave_size(shader); + unsigned gl_shader_stage = tgsi_processor_to_shader_stage(i); + record->shader_data[gl_shader_stage].hash[0] = _mesa_hash_data(code, shader->binary.uploaded_code_size); + record->shader_data[gl_shader_stage].hash[1] = record->shader_data[gl_shader_stage].hash[0]; + record->shader_data[gl_shader_stage].code_size = shader->binary.uploaded_code_size; + record->shader_data[gl_shader_stage].code = code; + record->shader_data[gl_shader_stage].vgpr_count = shader->config.num_vgprs; + record->shader_data[gl_shader_stage].sgpr_count = shader->config.num_sgprs; + record->shader_data[gl_shader_stage].base_address = va & 0xffffffffffff; + record->shader_data[gl_shader_stage].elf_symbol_offset = 0; + record->shader_data[gl_shader_stage].hw_stage = hw_stage; + record->shader_data[gl_shader_stage].is_combined = false; + record->shader_data[gl_shader_stage].scratch_memory_size = shader->config.scratch_bytes_per_wave; + record->shader_data[gl_shader_stage].wavefront_size = si_get_shader_wave_size(shader); - record->shader_stages_mask |= (1 << i); + record->shader_stages_mask |= 1 << gl_shader_stage; record->num_shaders_combined++; }