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ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
This commit is contained in:
Marek Olšák 2020-04-23 01:00:24 -04:00 committed by Marge Bot
parent f6d87ec8a9
commit 3dc2ccc14c
5 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/amd/common/ac_surface.c
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@ -661,7 +661,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
!AddrSurfInfoIn.flags.fmask &&
config->info.samples <= 1 &&
(surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
!(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
/* DCC notes:
* - If we add MSAA support, keep in mind that CB can't decompress 8bpp

4
src/amd/common/ac_surface.h
View File

@ -69,9 +69,11 @@ enum radeon_micro_mode {
#define RADEON_SURF_DISABLE_DCC (1 << 22)
/* gap */
#define RADEON_SURF_IMPORTED (1 << 24)
#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
/* gap */
#define RADEON_SURF_SHAREABLE (1 << 26)
#define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
/* Force a swizzle mode (gfx9+) or tile mode (gfx6-8).
* If this is not set, optimize for space. */
#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
#define RADEON_SURF_NO_FMASK (1 << 29)
#define RADEON_SURF_NO_HTILE (1 << 30)

2
src/amd/vulkan/radv_image.c
View File

@ -449,8 +449,6 @@ radv_init_surface(struct radv_device *device,
vk_format_is_compressed(image_format))
surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
surface->flags |= RADEON_SURF_DISABLE_DCC;

2
src/gallium/drivers/r600/r600_texture.c
View File

@ -243,8 +243,6 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
flags |= RADEON_SURF_SHAREABLE;
if (is_imported)
flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
r = rscreen->ws->surface_init(rscreen->ws, ptex,
flags, bpe, array_mode, surface);

8
src/gallium/drivers/radeonsi/si_texture.c
View File

@ -289,8 +289,6 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
flags |= RADEON_SURF_SHAREABLE;
if (is_imported)
flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
if (sscreen->debug_flags & DBG(NO_FMASK))
flags |= RADEON_SURF_NO_FMASK;
@ -299,9 +297,11 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags);
}
if (sscreen->info.chip_class >= GFX10 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
if (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING) {
flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X;
if (sscreen->info.chip_class >= GFX10)
surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X;
}
r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, array_mode, surface);