intel/fs: rework dss_id opcode into generic opcode
We'll want different types of IDs based on topology. Let's make this more flexible and also move the bit shifting code a layer above where it's easier to do bitshifting operations, especially if you need to stash things into temporary registers. v2: Keep previous comment. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
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@ -806,10 +806,11 @@ enum opcode {
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TES_OPCODE_CREATE_INPUT_READ_HEADER,
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TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
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SHADER_OPCODE_GET_DSS_ID,
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SHADER_OPCODE_BTD_SPAWN_LOGICAL,
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SHADER_OPCODE_BTD_RETIRE_LOGICAL,
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SHADER_OPCODE_READ_SR_REG,
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RT_OPCODE_TRACE_RAY_LOGICAL,
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};
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@ -2561,32 +2561,21 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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brw_float_controls_mode(p, src[0].d, src[1].d);
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break;
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case SHADER_OPCODE_GET_DSS_ID:
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/* The Slice, Dual-SubSlice, SubSlice, EU, and Thread IDs are all
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* stored in sr0.0. Normally, for reading from HW regs, we'd just do
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* this in the IR and let the back-end generate some code but these
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* live in the state register which tends to have special rules.
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*
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* For convenience, we combine Slice ID and Dual-SubSlice ID into a
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* single ID.
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*/
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if (devinfo->ver == 12) {
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case SHADER_OPCODE_READ_SR_REG:
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if (devinfo->ver >= 12) {
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/* There is a SWSB restriction that requires that any time sr0 is
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* accessed both the instruction doing the access and the next one
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* have SWSB set to RegDist(1).
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*/
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if (brw_get_default_swsb(p).mode != TGL_SBID_NULL)
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brw_SYNC(p, TGL_SYNC_NOP);
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assert(src[0].file == BRW_IMMEDIATE_VALUE);
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brw_set_default_swsb(p, tgl_swsb_regdist(1));
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brw_SHR(p, dst, brw_sr0_reg(0), brw_imm_ud(9));
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brw_MOV(p, dst, brw_sr0_reg(src[0].ud));
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brw_set_default_swsb(p, tgl_swsb_regdist(1));
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brw_AND(p, dst, dst, brw_imm_ud(0x1f));
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brw_AND(p, dst, dst, brw_imm_ud(0xffffffff));
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} else {
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/* These move around basically every hardware generation, so don't
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* do any >= checks and fail if the platform hasn't explicitly
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* been enabled here.
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*/
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unreachable("Unsupported platform");
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brw_MOV(p, dst, brw_sr0_reg(src[0].ud));
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}
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break;
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@ -5727,11 +5727,35 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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break;
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}
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case nir_intrinsic_load_topology_id_intel:
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assert(nir_intrinsic_base(instr) == BRW_TOPOLOGY_ID_DSS);
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bld.emit(SHADER_OPCODE_GET_DSS_ID,
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retype(dest, BRW_REGISTER_TYPE_UD));
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case nir_intrinsic_load_topology_id_intel: {
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/* These move around basically every hardware generation, so don'
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* do any >= checks and fail if the platform hasn't explicitly
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* been enabled here.
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*/
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assert(devinfo->ver == 12);
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/* Here is what the layout of SR0 looks like on Gfx12 :
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* [13:11] : Slice ID.
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* [10:9] : Dual-SubSlice ID
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* [8] : SubSlice ID
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* [7] : EUID[2] (aka EU Row ID)
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* [6] : Reserved
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* [5:4] : EUID[1:0]
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* [2:0] : Thread ID
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*/
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fs_reg raw_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.emit(SHADER_OPCODE_READ_SR_REG, raw_id, brw_imm_ud(0));
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switch (nir_intrinsic_base(instr)) {
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case BRW_TOPOLOGY_ID_DSS:
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bld.AND(raw_id, raw_id, brw_imm_ud(0x3fff));
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/* Get rid of anything below dualsubslice */
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bld.SHR(retype(dest, BRW_REGISTER_TYPE_UD), raw_id, brw_imm_ud(9));
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break;
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default:
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unreachable("Invalid topology id type");
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}
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break;
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}
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case nir_intrinsic_load_btd_stack_id_intel:
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if (stage == MESA_SHADER_COMPUTE) {
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@ -357,7 +357,7 @@ namespace {
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case TCS_OPCODE_SRC0_010_IS_ZERO:
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case TCS_OPCODE_GET_PRIMITIVE_ID:
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case TES_OPCODE_GET_PRIMITIVE_ID:
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case SHADER_OPCODE_GET_DSS_ID:
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case SHADER_OPCODE_READ_SR_REG:
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if (devinfo->ver >= 11) {
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return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2,
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0, 10, 6 /* XXX */, 14, 0, 0);
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@ -557,12 +557,12 @@ brw_instruction_name(const struct intel_device_info *devinfo, enum opcode op)
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return "rnd_mode";
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case SHADER_OPCODE_FLOAT_CONTROL_MODE:
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return "float_control_mode";
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case SHADER_OPCODE_GET_DSS_ID:
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return "get_dss_id";
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case SHADER_OPCODE_BTD_SPAWN_LOGICAL:
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return "btd_spawn_logical";
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case SHADER_OPCODE_BTD_RETIRE_LOGICAL:
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return "btd_retire_logical";
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case SHADER_OPCODE_READ_SR_REG:
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return "read_sr_reg";
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}
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unreachable("not reached");
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