ac/surface: move cmask_size/alignment into radeon_surf
cmask_size is changed to uint32_t because it can't be greater than 4GB. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
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@ -1286,8 +1286,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
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surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
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surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
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surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
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surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
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surf->u.gfx9.cmask_size = cout.cmaskBytes;
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surf->cmask_size = cout.cmaskBytes;
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surf->u.gfx9.cmask_alignment = cout.baseAlign;
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surf->cmask_alignment = cout.baseAlign;
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}
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}
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}
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}
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@ -1428,7 +1428,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
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surf->htile_slice_size = 0;
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surf->htile_slice_size = 0;
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surf->u.gfx9.surf_offset = 0;
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surf->u.gfx9.surf_offset = 0;
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surf->u.gfx9.stencil_offset = 0;
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surf->u.gfx9.stencil_offset = 0;
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surf->u.gfx9.cmask_size = 0;
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surf->cmask_size = 0;
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/* Calculate texture layout information. */
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/* Calculate texture layout information. */
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r = gfx9_compute_miptree(addrlib, config, surf, compressed,
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r = gfx9_compute_miptree(addrlib, config, surf, compressed,
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@ -150,9 +150,6 @@ struct gfx9_surf_layout {
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uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */
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uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */
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uint64_t stencil_offset; /* separate stencil */
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uint64_t stencil_offset; /* separate stencil */
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uint64_t cmask_size;
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uint32_t cmask_alignment;
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};
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};
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struct radeon_surf {
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struct radeon_surf {
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@ -196,17 +193,20 @@ struct radeon_surf {
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uint64_t surf_size;
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uint64_t surf_size;
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uint64_t fmask_size;
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uint64_t fmask_size;
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/* DCC and HTILE are very small. */
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uint32_t dcc_size;
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uint32_t htile_size;
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uint32_t htile_slice_size;
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uint32_t surf_alignment;
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uint32_t surf_alignment;
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uint32_t fmask_alignment;
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uint32_t fmask_alignment;
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/* DCC and HTILE are very small. */
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uint32_t dcc_size;
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uint32_t dcc_alignment;
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uint32_t dcc_alignment;
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uint32_t htile_size;
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uint32_t htile_slice_size;
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uint32_t htile_alignment;
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uint32_t htile_alignment;
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uint32_t cmask_size;
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uint32_t cmask_alignment;
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union {
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union {
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/* R600-VI return values.
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/* R600-VI return values.
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*
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*
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@ -772,8 +772,8 @@ radv_image_get_cmask_info(struct radv_device *device,
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unsigned cl_width, cl_height;
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unsigned cl_width, cl_height;
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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out->alignment = image->surface.u.gfx9.cmask_alignment;
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out->alignment = image->surface.cmask_alignment;
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out->size = image->surface.u.gfx9.cmask_size;
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out->size = image->surface.cmask_size;
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return;
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return;
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}
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}
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@ -1050,11 +1050,11 @@ void si_print_texture_info(struct si_screen *sscreen,
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}
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}
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if (tex->cmask.size) {
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if (tex->cmask.size) {
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u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", "
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u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, "
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"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
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"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
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tex->cmask.offset,
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tex->cmask.offset,
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tex->surface.u.gfx9.cmask_size,
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tex->surface.cmask_size,
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tex->surface.u.gfx9.cmask_alignment,
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tex->surface.cmask_alignment,
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tex->surface.u.gfx9.cmask.rb_aligned,
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tex->surface.u.gfx9.cmask.rb_aligned,
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tex->surface.u.gfx9.cmask.pipe_aligned);
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tex->surface.u.gfx9.cmask.pipe_aligned);
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}
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}
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