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i965/icl: Set use full ways in L3CNTLREG 

L3 allocation table in h/w specification recommends using 4 KB
granularity for programming allocation fields in L3CNTLREG.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Anuj Phogat 2018-10-11 10:52:16 -07:00
parent 3282c7be89
commit 3ce04da5b4
2 changed files with 2 additions and 0 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
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@ -1647,6 +1647,7 @@ enum brw_pixel_shader_coverage_mask_mode {
# define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25
# define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
# define GEN8_L3CNTLREG_EDBC_NO_HANG (1 << 9)
# define GEN11_L3CNTLREG_USE_FULL_WAYS (1 << 10)
#define GEN10_CACHE_MODE_SS 0x0e420
#define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)

1
src/mesa/drivers/dri/i965/gen7_l3_state.c
View File

@ -119,6 +119,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
(devinfo->gen == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) |
SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |