From 3cafa3e852c517a6dc6f53a6ffdda1ab969b0636 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 13 Jan 2022 02:35:08 -0500 Subject: [PATCH] ac/surface: allow displayable DCC with any resolution (e.g. 8K) Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_surface.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 187b9599358..9be16b33789 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1490,6 +1490,12 @@ static bool gfx10_DCN_requires_independent_64B_blocks(const struct radeon_info * void ac_modifier_max_extent(const struct radeon_info *info, uint64_t modifier, uint32_t *width, uint32_t *height) { + /* DCC is supported with any size. The maximum width per display pipe is 5760, but multiple + * display pipes can be used to drive the display. + */ + *width = 16384; + *height = 16384; + if (ac_modifier_has_dcc(modifier)) { bool independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); @@ -1497,15 +1503,7 @@ void ac_modifier_max_extent(const struct radeon_info *info, /* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B. */ *width = 2560; *height = 2560; - } else { - /* DCC is not supported on surfaces above resolutions af 5760. */ - *width = 5760; - *height = 5760; } - } else { - /* Non-dcc modifiers */ - *width = 16384; - *height = 16384; } } @@ -1525,10 +1523,6 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info, if (info->use_display_dcc_unaligned && (rb_aligned || pipe_aligned)) return false; - /* Big resolutions don't support DCC. */ - if (config->info.width > 5760 || config->info.height > 5760) - return false; - switch (info->chip_class) { case GFX6: case GFX7: