From 3c96880e13151a78097a2ea334e9fbb3de38a114 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 9 Mar 2021 10:43:04 -0800 Subject: [PATCH] freedreno/a5xx: Introduce an event write helper like a6xx has. This should help the next person trying to diff a5xx to a6xx behavior. Part-of: --- src/gallium/drivers/freedreno/a5xx/fd5_draw.c | 9 +++-- src/gallium/drivers/freedreno/a5xx/fd5_emit.h | 26 ++++++++------ src/gallium/drivers/freedreno/a5xx/fd5_gmem.c | 35 +++++++------------ .../drivers/freedreno/a5xx/fd5_query.c | 7 ++-- 4 files changed, 34 insertions(+), 43 deletions(-) diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c index 5d6891646a2..0f372b77913 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c @@ -130,8 +130,7 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info, for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) { if (emit.streamout_mask & (1 << i)) { - OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, FLUSH_SO_0 + i); + fd5_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false); } } } @@ -220,7 +219,7 @@ fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) | A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1)); - fd5_emit_blit(batch->ctx, ring); + fd5_emit_blit(batch, ring); } static bool @@ -293,7 +292,7 @@ fd5_clear(struct fd_context *ctx, unsigned buffers, OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */ OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */ - fd5_emit_blit(ctx, ring); + fd5_emit_blit(ctx->batch, ring); } } @@ -318,7 +317,7 @@ fd5_clear(struct fd_context *ctx, unsigned buffers, OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1); OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */ - fd5_emit_blit(ctx, ring); + fd5_emit_blit(ctx->batch, ring); if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) { struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture); diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h index 42bc88d89a4..44f32357414 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h +++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h @@ -134,17 +134,22 @@ fd5_set_render_mode(struct fd_context *ctx, struct fd_ringbuffer *ring, } static inline void -fd5_emit_blit(struct fd_context *ctx, struct fd_ringbuffer *ring) +fd5_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring, + enum vgt_event_type evt, bool timestamp) { - struct fd5_context *fd5_ctx = fd5_context(ctx); + OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1); + OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt)); + if (timestamp) { + OUT_RELOC(ring, fd5_context(batch->ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */ + OUT_RING(ring, 0x00000000); + } +} +static inline void +fd5_emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring) +{ emit_marker5(ring, 7); - - OUT_PKT7(ring, CP_EVENT_WRITE, 4); - OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(BLIT)); - OUT_RELOC(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */ - OUT_RING(ring, 0x00000000); - + fd5_event_write(batch, ring, BLIT, true); emit_marker5(ring, 7); } @@ -177,7 +182,7 @@ fd5_emit_render_cntl(struct fd_context *ctx, bool blit, bool binning) } static inline void -fd5_emit_lrz_flush(struct fd_ringbuffer *ring) +fd5_emit_lrz_flush(struct fd_batch *batch, struct fd_ringbuffer *ring) { /* TODO I think the extra writes to GRAS_LRZ_CNTL are probably * a workaround and not needed on all a5xx. @@ -185,8 +190,7 @@ fd5_emit_lrz_flush(struct fd_ringbuffer *ring) OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); OUT_RING(ring, A5XX_GRAS_LRZ_CNTL_ENABLE); - OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, LRZ_FLUSH); + fd5_event_write(batch, ring, LRZ_FLUSH, false); OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); OUT_RING(ring, 0x0); diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c index 40c34c57c84..9cb8717c836 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c @@ -302,7 +302,6 @@ static void emit_binning_pass(struct fd_batch *batch) assert_dt { - struct fd_context *ctx = batch->ctx; struct fd_ringbuffer *ring = batch->gmem; const struct fd_gmem_stateobj *gmem = batch->gmem_state; @@ -334,8 +333,7 @@ emit_binning_pass(struct fd_batch *batch) OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1); OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS); - OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, UNK_2C); + fd5_event_write(batch, ring, UNK_2C, false); OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1); OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) | @@ -346,13 +344,9 @@ emit_binning_pass(struct fd_batch *batch) fd_reset_wfi(batch); - OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, UNK_2D); + fd5_event_write(batch, ring, UNK_2D, false); - OUT_PKT7(ring, CP_EVENT_WRITE, 4); - OUT_RING(ring, CACHE_FLUSH_TS); - OUT_RELOC(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */ - OUT_RING(ring, 0x00000000); + fd5_event_write(batch, ring, CACHE_FLUSH_TS, true); // TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??) @@ -375,7 +369,7 @@ fd5_emit_tile_init(struct fd_batch *batch) if (batch->prologue) fd5_emit_ib(ring, batch->prologue); - fd5_emit_lrz_flush(ring); + fd5_emit_lrz_flush(batch, ring); OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1); OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */ @@ -399,7 +393,7 @@ fd5_emit_tile_init(struct fd_batch *batch) if (use_hw_binning(batch)) { emit_binning_pass(batch); - fd5_emit_lrz_flush(ring); + fd5_emit_lrz_flush(batch, ring); patch_draws(batch, USE_VISIBILITY); } else { patch_draws(batch, IGNORE_VISIBILITY); @@ -519,7 +513,7 @@ emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base, OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1); OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf)); - fd5_emit_blit(batch->ctx, ring); + fd5_emit_blit(batch, ring); } static void @@ -649,7 +643,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base, OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1); OUT_RING(ring, COND(msaa_resolve, A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE)); - fd5_emit_blit(batch->ctx, ring); + fd5_emit_blit(batch, ring); } static void @@ -689,7 +683,7 @@ fd5_emit_tile_fini(struct fd_batch *batch) OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); OUT_RING(ring, 0x0); - fd5_emit_lrz_flush(ring); + fd5_emit_lrz_flush(batch, ring); fd5_cache_flush(batch, ring); fd5_set_render_mode(batch->ctx, ring, BYPASS); @@ -703,7 +697,7 @@ fd5_emit_sysmem_prep(struct fd_batch *batch) fd5_emit_restore(batch, ring); - fd5_emit_lrz_flush(ring); + fd5_emit_lrz_flush(batch, ring); if (batch->prologue) fd5_emit_ib(ring, batch->prologue); @@ -711,8 +705,7 @@ fd5_emit_sysmem_prep(struct fd_batch *batch) OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); OUT_RING(ring, 0x0); - OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, PC_CCU_INVALIDATE_COLOR); + fd5_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false); OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1); OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */ @@ -779,18 +772,14 @@ fd5_emit_sysmem_prep(struct fd_batch *batch) static void fd5_emit_sysmem_fini(struct fd_batch *batch) { - struct fd5_context *fd5_ctx = fd5_context(batch->ctx); struct fd_ringbuffer *ring = batch->gmem; OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); OUT_RING(ring, 0x0); - fd5_emit_lrz_flush(ring); + fd5_emit_lrz_flush(batch, ring); - OUT_PKT7(ring, CP_EVENT_WRITE, 4); - OUT_RING(ring, PC_CCU_FLUSH_COLOR_TS); - OUT_RELOC(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */ - OUT_RING(ring, 0x00000000); + fd5_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true); } void diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_query.c b/src/gallium/drivers/freedreno/a5xx/fd5_query.c index 8547c5a2736..fc8251e8fd2 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_query.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_query.c @@ -30,6 +30,7 @@ #include "freedreno_resource.h" #include "fd5_context.h" +#include "fd5_emit.h" #include "fd5_format.h" #include "fd5_query.h" @@ -68,8 +69,7 @@ occlusion_resume(struct fd_acc_query *aq, struct fd_batch *batch) OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2); OUT_RELOC(ring, query_sample(aq, start)); - OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, ZPASS_DONE); + fd5_event_write(batch, ring, ZPASS_DONE, false); fd_reset_wfi(batch); fd5_context(batch->ctx)->samples_passed_queries++; @@ -93,8 +93,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch) OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2); OUT_RELOC(ring, query_sample(aq, stop)); - OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, ZPASS_DONE); + fd5_event_write(batch, ring, ZPASS_DONE, false); fd_reset_wfi(batch); OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);