i965/vec4: Add basic common subexpression elimination.
[mattst88]: Modified to perform CSE on instructions with
the same writemask. Offered no improvement before.
total instructions in shared programs: 1995633 -> 1995185 (-0.02%)
instructions in affected programs: 14410 -> 13962 (-3.11%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Kenneth Graunke
Matt Turner
parent
848fc7f710
commit
3c8dc48ad1
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@ -102,6 +102,7 @@ i965_FILES = \
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brw_util.c \
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brw_vec4.cpp \
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brw_vec4_copy_propagation.cpp \
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brw_vec4_cse.cpp \
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brw_vec4_generator.cpp \
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brw_vec4_gs.c \
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brw_vec4_gs_visitor.cpp \
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@ -1675,6 +1675,7 @@ vec4_visitor::run()
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progress = dead_control_flow_eliminate(this) || progress;
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progress = opt_copy_propagation() || progress;
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progress = opt_algebraic() || progress;
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progress = opt_cse() || progress;
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progress = opt_register_coalesce() || progress;
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} while (progress);
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@ -384,6 +384,8 @@ public:
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bool dead_code_eliminate();
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bool virtual_grf_interferes(int a, int b);
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bool opt_copy_propagation();
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bool opt_cse_local(bblock_t *, exec_list *);
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bool opt_cse();
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bool opt_algebraic();
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bool opt_register_coalesce();
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void opt_set_dependency_control();
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@ -0,0 +1,232 @@
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/*
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* Copyright © 2012, 2013, 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_vec4.h"
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#include "brw_cfg.h"
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using namespace brw;
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/** @file brw_vec4_cse.cpp
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*
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* Support for local common subexpression elimination.
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*
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* See Muchnick's Advanced Compiler Design and Implementation, section
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* 13.1 (p378).
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*/
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namespace {
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struct aeb_entry : public exec_node {
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/** The instruction that generates the expression value. */
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vec4_instruction *generator;
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/** The temporary where the value is stored. */
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src_reg tmp;
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};
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}
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static bool
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is_expression(const vec4_instruction *const inst)
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{
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switch (inst->opcode) {
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case BRW_OPCODE_SEL:
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case BRW_OPCODE_NOT:
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case BRW_OPCODE_AND:
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case BRW_OPCODE_OR:
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case BRW_OPCODE_XOR:
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case BRW_OPCODE_SHR:
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case BRW_OPCODE_SHL:
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case BRW_OPCODE_ASR:
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case BRW_OPCODE_ADD:
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case BRW_OPCODE_MUL:
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case BRW_OPCODE_FRC:
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case BRW_OPCODE_RNDU:
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case BRW_OPCODE_RNDD:
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case BRW_OPCODE_RNDE:
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case BRW_OPCODE_RNDZ:
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case BRW_OPCODE_LINE:
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case BRW_OPCODE_PLN:
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case BRW_OPCODE_MAD:
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case BRW_OPCODE_LRP:
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return true;
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SQRT:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_LOG2:
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case SHADER_OPCODE_POW:
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case SHADER_OPCODE_INT_QUOTIENT:
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case SHADER_OPCODE_INT_REMAINDER:
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_COS:
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return inst->mlen == 0;
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default:
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return false;
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}
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}
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static bool
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is_expression_commutative(enum opcode op)
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{
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switch (op) {
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case BRW_OPCODE_AND:
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case BRW_OPCODE_OR:
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case BRW_OPCODE_XOR:
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case BRW_OPCODE_ADD:
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case BRW_OPCODE_MUL:
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return true;
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default:
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return false;
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}
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}
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static bool
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operands_match(enum opcode op, src_reg *xs, src_reg *ys)
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{
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if (!is_expression_commutative(op)) {
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return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
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} else {
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return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
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(xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
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}
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}
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static bool
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instructions_match(vec4_instruction *a, vec4_instruction *b)
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{
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return a->opcode == b->opcode &&
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a->saturate == b->saturate &&
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a->conditional_mod == b->conditional_mod &&
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a->dst.type == b->dst.type &&
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a->dst.writemask == b->dst.writemask &&
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operands_match(a->opcode, a->src, b->src);
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}
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bool
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vec4_visitor::opt_cse_local(bblock_t *block, exec_list *aeb)
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{
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bool progress = false;
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void *cse_ctx = ralloc_context(NULL);
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for (vec4_instruction *inst = (vec4_instruction *)block->start;
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inst != block->end->next;
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inst = (vec4_instruction *) inst->next) {
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/* Skip some cases. */
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if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
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!inst->conditional_mod)
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{
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bool found = false;
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foreach_in_list_use_after(aeb_entry, entry, aeb) {
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/* Match current instruction's expression against those in AEB. */
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if (instructions_match(inst, entry->generator)) {
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found = true;
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progress = true;
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break;
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}
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}
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if (!found) {
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/* Our first sighting of this expression. Create an entry. */
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aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
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entry->tmp = src_reg(); /* file will be BAD_FILE */
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entry->generator = inst;
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aeb->push_tail(entry);
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} else {
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/* This is at least our second sighting of this expression.
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* If we don't have a temporary already, make one.
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*/
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bool no_existing_temp = entry->tmp.file == BAD_FILE;
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if (no_existing_temp) {
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entry->tmp = src_reg(this, glsl_type::float_type);
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entry->tmp.type = inst->dst.type;
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entry->tmp.swizzle = BRW_SWIZZLE_XYZW;
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vec4_instruction *copy = MOV(entry->generator->dst, entry->tmp);
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entry->generator->insert_after(copy);
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entry->generator->dst = dst_reg(entry->tmp);
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}
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/* dest <- temp */
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assert(inst->dst.type == entry->tmp.type);
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vec4_instruction *copy = MOV(inst->dst, entry->tmp);
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copy->force_writemask_all = inst->force_writemask_all;
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inst->insert_before(copy);
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/* Set our iterator so that next time through the loop inst->next
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* will get the instruction in the basic block after the one we've
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* removed.
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*/
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vec4_instruction *prev = (vec4_instruction *)inst->prev;
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inst->remove();
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/* Appending an instruction may have changed our bblock end. */
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if (inst == block->end) {
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block->end = prev;
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}
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inst = prev;
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}
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}
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foreach_in_list_safe(aeb_entry, entry, aeb) {
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for (int i = 0; i < 3; i++) {
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/* Kill all AEB entries that use the destination we just
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* overwrote.
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*/
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if (inst->dst.file == entry->generator->src[i].file &&
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inst->dst.reg == entry->generator->src[i].reg) {
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entry->remove();
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ralloc_free(entry);
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break;
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}
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}
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}
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}
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ralloc_free(cse_ctx);
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if (progress)
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invalidate_live_intervals();
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return progress;
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}
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bool
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vec4_visitor::opt_cse()
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{
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bool progress = false;
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cfg_t cfg(&instructions);
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for (int b = 0; b < cfg.num_blocks; b++) {
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bblock_t *block = cfg.blocks[b];
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exec_list aeb;
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progress = opt_cse_local(block, &aeb) || progress;
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}
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return progress;
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}
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