radeonsi: rename dma_cs -> sdma_cs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
This commit is contained in:
parent
cd6a4f7631
commit
3c265c2586
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@ -33,7 +33,7 @@ static void cik_sdma_copy_buffer(struct si_context *ctx,
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uint64_t src_offset,
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uint64_t size)
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{
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struct radeon_cmdbuf *cs = ctx->dma_cs;
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struct radeon_cmdbuf *cs = ctx->sdma_cs;
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unsigned i, ncopy, csize;
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unsigned align = ~0u;
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struct si_resource *sdst = si_resource(dst);
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@ -162,7 +162,7 @@ static bool si_sdma_v4_copy_texture(struct si_context *sctx,
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/* Linear -> linear sub-window copy. */
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if (ssrc->surface.is_linear &&
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sdst->surface.is_linear) {
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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/* Check if everything fits into the bitfields */
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if (!(src_pitch <= (1 << 19) &&
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@ -228,7 +228,7 @@ static bool si_sdma_v4_copy_texture(struct si_context *sctx,
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unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
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uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
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uint64_t linear_address = linear == ssrc ? src_address : dst_address;
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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linear_address += linear->surface.u.gfx9.offset[linear_level];
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@ -381,7 +381,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
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sctx->family != CHIP_KAVERI) ||
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(srcx + copy_width != (1 << 14) &&
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srcy + copy_height != (1 << 14)))) {
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
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@ -542,7 +542,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
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copy_width_aligned <= (1 << 14) &&
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copy_height <= (1 << 14) &&
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copy_depth <= (1 << 11)) {
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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uint32_t direction = linear == sdst ? 1u << 31 : 0;
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si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
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@ -636,7 +636,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
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(srcx + copy_width_aligned != (1 << 14) &&
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srcy + copy_height_aligned != (1 << 14) &&
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dstx + copy_width != (1 << 14)))) {
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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si_need_dma_space(sctx, 15, &sdst->buffer, &ssrc->buffer);
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@ -680,7 +680,7 @@ static void cik_sdma_copy(struct pipe_context *ctx,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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if (!sctx->dma_cs ||
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if (!sctx->sdma_cs ||
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src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
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dst->flags & PIPE_RESOURCE_FLAG_SPARSE)
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goto fallback;
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@ -36,8 +36,8 @@ bool si_rings_is_buffer_referenced(struct si_context *sctx,
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if (sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs, buf, usage)) {
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return true;
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}
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if (radeon_emitted(sctx->dma_cs, 0) &&
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sctx->ws->cs_is_buffer_referenced(sctx->dma_cs, buf, usage)) {
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if (radeon_emitted(sctx->sdma_cs, 0) &&
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sctx->ws->cs_is_buffer_referenced(sctx->sdma_cs, buf, usage)) {
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return true;
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}
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return false;
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@ -72,8 +72,8 @@ void *si_buffer_map_sync_with_rings(struct si_context *sctx,
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busy = true;
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}
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}
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if (radeon_emitted(sctx->dma_cs, 0) &&
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sctx->ws->cs_is_buffer_referenced(sctx->dma_cs,
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if (radeon_emitted(sctx->sdma_cs, 0) &&
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sctx->ws->cs_is_buffer_referenced(sctx->sdma_cs,
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resource->buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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si_flush_dma_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
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@ -91,8 +91,8 @@ void *si_buffer_map_sync_with_rings(struct si_context *sctx,
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/* We will be wait for the GPU. Wait for any offloaded
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* CS flush to complete to avoid busy-waiting in the winsys. */
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sctx->ws->cs_sync_flush(sctx->gfx_cs);
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if (sctx->dma_cs)
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sctx->ws->cs_sync_flush(sctx->dma_cs);
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if (sctx->sdma_cs)
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sctx->ws->cs_sync_flush(sctx->sdma_cs);
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}
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}
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@ -791,13 +791,13 @@ static bool si_resource_commit(struct pipe_context *pctx,
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res->buf, RADEON_USAGE_READWRITE)) {
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si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
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}
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if (radeon_emitted(ctx->dma_cs, 0) &&
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ctx->ws->cs_is_buffer_referenced(ctx->dma_cs,
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if (radeon_emitted(ctx->sdma_cs, 0) &&
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ctx->ws->cs_is_buffer_referenced(ctx->sdma_cs,
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res->buf, RADEON_USAGE_READWRITE)) {
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si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
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}
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ctx->ws->cs_sync_flush(ctx->dma_cs);
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ctx->ws->cs_sync_flush(ctx->sdma_cs);
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ctx->ws->cs_sync_flush(ctx->gfx_cs);
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assert(resource->target == PIPE_BUFFER);
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@ -35,7 +35,7 @@ static void si_dma_copy_buffer(struct si_context *ctx,
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uint64_t src_offset,
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uint64_t size)
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{
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struct radeon_cmdbuf *cs = ctx->dma_cs;
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struct radeon_cmdbuf *cs = ctx->sdma_cs;
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unsigned i, ncopy, count, max_size, sub_cmd, shift;
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struct si_resource *sdst = si_resource(dst);
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struct si_resource *ssrc = si_resource(src);
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@ -87,7 +87,7 @@ static void si_dma_copy(struct pipe_context *ctx,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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if (sctx->dma_cs == NULL ||
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if (sctx->sdma_cs == NULL ||
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src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
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dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
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goto fallback;
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@ -27,7 +27,7 @@
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static void si_dma_emit_wait_idle(struct si_context *sctx)
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{
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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/* NOP waits for idle. */
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if (sctx->chip_class >= GFX7)
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@ -39,7 +39,7 @@ static void si_dma_emit_wait_idle(struct si_context *sctx)
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void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
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uint64_t offset)
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{
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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uint64_t va = dst->gpu_address + offset;
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if (sctx->chip_class == GFX6) {
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@ -67,7 +67,7 @@ void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
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void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
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uint64_t offset, uint64_t size, unsigned clear_value)
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{
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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struct radeon_cmdbuf *cs = sctx->sdma_cs;
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unsigned i, ncopy, csize;
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struct si_resource *sdst = si_resource(dst);
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@ -129,8 +129,8 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
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struct si_resource *dst, struct si_resource *src)
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{
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struct radeon_winsys *ws = ctx->ws;
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uint64_t vram = ctx->dma_cs->used_vram;
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uint64_t gtt = ctx->dma_cs->used_gart;
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uint64_t vram = ctx->sdma_cs->used_vram;
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uint64_t gtt = ctx->sdma_cs->used_gart;
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if (dst) {
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vram += dst->vram_usage;
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@ -166,31 +166,31 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
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*/
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num_dw++; /* for emit_wait_idle below */
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if (!ctx->sdma_uploads_in_progress &&
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(!ws->cs_check_space(ctx->dma_cs, num_dw, false) ||
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ctx->dma_cs->used_vram + ctx->dma_cs->used_gart > 64 * 1024 * 1024 ||
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!radeon_cs_memory_below_limit(ctx->screen, ctx->dma_cs, vram, gtt))) {
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(!ws->cs_check_space(ctx->sdma_cs, num_dw, false) ||
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ctx->sdma_cs->used_vram + ctx->sdma_cs->used_gart > 64 * 1024 * 1024 ||
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!radeon_cs_memory_below_limit(ctx->screen, ctx->sdma_cs, vram, gtt))) {
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si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
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assert((num_dw + ctx->dma_cs->current.cdw) <= ctx->dma_cs->current.max_dw);
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assert((num_dw + ctx->sdma_cs->current.cdw) <= ctx->sdma_cs->current.max_dw);
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}
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/* Wait for idle if either buffer has been used in the IB before to
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* prevent read-after-write hazards.
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*/
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if ((dst &&
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ws->cs_is_buffer_referenced(ctx->dma_cs, dst->buf,
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ws->cs_is_buffer_referenced(ctx->sdma_cs, dst->buf,
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RADEON_USAGE_READWRITE)) ||
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(src &&
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ws->cs_is_buffer_referenced(ctx->dma_cs, src->buf,
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ws->cs_is_buffer_referenced(ctx->sdma_cs, src->buf,
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RADEON_USAGE_WRITE)))
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si_dma_emit_wait_idle(ctx);
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unsigned sync = ctx->sdma_uploads_in_progress ? 0 : RADEON_USAGE_SYNCHRONIZED;
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if (dst) {
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ws->cs_add_buffer(ctx->dma_cs, dst->buf, RADEON_USAGE_WRITE | sync,
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ws->cs_add_buffer(ctx->sdma_cs, dst->buf, RADEON_USAGE_WRITE | sync,
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dst->domains, 0);
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}
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if (src) {
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ws->cs_add_buffer(ctx->dma_cs, src->buf, RADEON_USAGE_READ | sync,
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ws->cs_add_buffer(ctx->sdma_cs, src->buf, RADEON_USAGE_READ | sync,
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src->domains, 0);
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}
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@ -201,7 +201,7 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
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void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
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struct pipe_fence_handle **fence)
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{
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struct radeon_cmdbuf *cs = ctx->dma_cs;
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struct radeon_cmdbuf *cs = ctx->sdma_cs;
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struct radeon_saved_cs saved;
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bool check_vm = (ctx->screen->debug_flags & DBG(CHECK_VM)) != 0;
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@ -180,8 +180,8 @@ static void si_add_fence_dependency(struct si_context *sctx,
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{
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struct radeon_winsys *ws = sctx->ws;
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if (sctx->dma_cs)
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ws->cs_add_fence_dependency(sctx->dma_cs, fence, 0);
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if (sctx->sdma_cs)
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ws->cs_add_fence_dependency(sctx->sdma_cs, fence, 0);
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ws->cs_add_fence_dependency(sctx->gfx_cs, fence, 0);
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}
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@ -513,7 +513,7 @@ static void si_flush_from_st(struct pipe_context *ctx,
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}
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/* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
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if (sctx->dma_cs)
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if (sctx->sdma_cs)
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si_flush_dma_cs(sctx, rflags, fence ? &sdma_fence : NULL);
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if (!radeon_emitted(sctx->gfx_cs, sctx->initial_gfx_cs_size)) {
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@ -577,8 +577,8 @@ static void si_flush_from_st(struct pipe_context *ctx,
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assert(!fine.buf);
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finish:
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if (!(flags & (PIPE_FLUSH_DEFERRED | PIPE_FLUSH_ASYNC))) {
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if (sctx->dma_cs)
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ws->cs_sync_flush(sctx->dma_cs);
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if (sctx->sdma_cs)
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ws->cs_sync_flush(sctx->sdma_cs);
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ws->cs_sync_flush(sctx->gfx_cs);
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}
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}
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@ -110,7 +110,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
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* If the driver flushes the GFX IB internally, and it should never ask
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* for a fence handle.
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*/
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assert(!radeon_emitted(ctx->dma_cs, 0) || fence == NULL);
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assert(!radeon_emitted(ctx->sdma_cs, 0) || fence == NULL);
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/* Update the sdma_uploads list by flushing the uploader. */
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u_upload_unmap(ctx->b.const_uploader);
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@ -132,7 +132,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
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si_unref_sdma_uploads(ctx);
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/* Flush SDMA (preamble IB). */
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if (radeon_emitted(ctx->dma_cs, 0))
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if (radeon_emitted(ctx->sdma_cs, 0))
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si_flush_dma_cs(ctx, flags, NULL);
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if (radeon_emitted(ctx->prim_discard_compute_cs, 0)) {
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@ -270,8 +270,8 @@ static void si_destroy_context(struct pipe_context *context)
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if (sctx->gfx_cs)
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sctx->ws->cs_destroy(sctx->gfx_cs);
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if (sctx->dma_cs)
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sctx->ws->cs_destroy(sctx->dma_cs);
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if (sctx->sdma_cs)
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sctx->ws->cs_destroy(sctx->sdma_cs);
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if (sctx->ctx)
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sctx->ws->ctx_destroy(sctx->ctx);
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@ -494,12 +494,12 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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* https://gitlab.freedesktop.org/mesa/mesa/issues/1907
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*/
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(sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) {
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sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
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sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
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(void*)si_flush_dma_cs,
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sctx, stop_exec_on_failure);
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}
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bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
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bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs;
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sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
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0, PIPE_USAGE_DEFAULT,
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SI_RESOURCE_FLAG_32BIT |
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@ -865,7 +865,7 @@ struct si_context {
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struct radeon_winsys *ws;
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struct radeon_winsys_ctx *ctx;
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struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
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struct radeon_cmdbuf *dma_cs;
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struct radeon_cmdbuf *sdma_cs;
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struct pipe_fence_handle *last_gfx_fence;
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struct pipe_fence_handle *last_sdma_fence;
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struct si_resource *eop_bug_scratch;
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@ -112,7 +112,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
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unsigned cs_dwords_per_thread =
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test_cs ? cs_dwords_per_thread_list[cs_method % NUM_SHADERS] : 0;
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if (test_sdma && !sctx->dma_cs)
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if (test_sdma && !sctx->sdma_cs)
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continue;
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if (sctx->chip_class == GFX6) {
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@ -53,7 +53,7 @@ bool si_prepare_for_dma_blit(struct si_context *sctx,
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unsigned src_level,
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const struct pipe_box *src_box)
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{
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if (!sctx->dma_cs)
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if (!sctx->sdma_cs)
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return false;
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if (dst->surface.bpe != src->surface.bpe)
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