KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

radeon/llvm: Encapsulate setting of MachineOperand flags 

MachineOperand flags will be removed soon, so it is convienent to
have only one function that modifies them.
This commit is contained in:
Tom Stellard 2012-08-21 19:30:26 +00:00
parent bee2edbf3d
commit 3a7a56e7aa
4 changed files with 70 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp
View File

@ -146,14 +146,13 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
} else {
Opcode = MI.getOpcode();
}
MachineOperand NewDstOp = MachineOperand::CreateReg(DstReg, true);
NewDstOp.addTargetFlag(Flags);
MachineInstr *NewMI =
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
.addReg(Src0)
.addReg(Src1);
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode))
.addOperand(NewDstOp)
.addReg(Src0)
.addReg(Src1)
->setIsInsideBundle(Chan != 0);
NewMI->setIsInsideBundle(Chan != 0);
TII->AddFlag(NewMI, 0, Flags);
}
MI.eraseFromParent();
}

93
src/gallium/drivers/radeon/R600ISelLowering.cpp
View File

@ -59,28 +59,36 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
switch (MI->getOpcode()) {
default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
case AMDGPU::CLAMP_R600:
MI->getOperand(0).addTargetFlag(MO_FLAG_CLAMP);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::PRED_SEL_OFF);
break;
{
MachineInstr *NewMI =
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::PRED_SEL_OFF);
TII->AddFlag(NewMI, 0, MO_FLAG_CLAMP);
break;
}
case AMDGPU::FABS_R600:
MI->getOperand(1).addTargetFlag(MO_FLAG_ABS);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::PRED_SEL_OFF);
break;
{
MachineInstr *NewMI =
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::PRED_SEL_OFF);
TII->AddFlag(NewMI, 1, MO_FLAG_ABS);
break;
}
case AMDGPU::FNEG_R600:
MI->getOperand(1).addTargetFlag(MO_FLAG_NEG);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::PRED_SEL_OFF);
{
MachineInstr *NewMI =
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addReg(AMDGPU::PRED_SEL_OFF);
TII->AddFlag(NewMI, 1, MO_FLAG_NEG);
break;
}
case AMDGPU::R600_LOAD_CONST:
{
@ -97,8 +105,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
unsigned maskedRegister = MI->getOperand(0).getReg();
assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
MachineOperand * def = defInstr->findRegisterDefOperand(maskedRegister);
def->addTargetFlag(MO_FLAG_MASK);
TII->AddFlag(defInstr, 0, MO_FLAG_MASK);
// Return early so the instruction is not erased
return BB;
}
@ -188,29 +195,31 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
.addReg(0);
break;
case AMDGPU::BRANCH_COND_f32:
MI->getOperand(1).addTargetFlag(MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
.addReg(AMDGPU::PREDICATE_BIT)
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_ZERO);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
.addOperand(MI->getOperand(0))
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
break;
{
MachineInstr *NewMI =
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
.addReg(AMDGPU::PREDICATE_BIT)
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_ZERO);
TII->AddFlag(NewMI, 1, MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
.addOperand(MI->getOperand(0))
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
break;
}
case AMDGPU::BRANCH_COND_i32:
MI->getOperand(1).addTargetFlag(MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
.addReg(AMDGPU::PREDICATE_BIT)
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_ZERO_INT);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
.addOperand(MI->getOperand(0))
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
break;
{
MachineInstr *NewMI =
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
.addReg(AMDGPU::PREDICATE_BIT)
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_ZERO_INT);
TII->AddFlag(NewMI, 1, MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
.addOperand(MI->getOperand(0))
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
break;
}
}
MI->eraseFromParent();

10
src/gallium/drivers/radeon/R600InstrInfo.cpp
View File

@ -518,3 +518,13 @@ int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
*PredCost = 2;
return 2;
}
//===----------------------------------------------------------------------===//
// Instruction flag setters
//===----------------------------------------------------------------------===//
void R600InstrInfo::AddFlag(MachineInstr *MI, unsigned Operand,
unsigned Flag) const
{
MI->getOperand(Operand).addTargetFlag(Flag);
}

3
src/gallium/drivers/radeon/R600InstrInfo.h
View File

@ -111,6 +111,9 @@ namespace llvm {
virtual int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const { return 1;}
///AddFlag - Add one of the MO_FLAG* flags to the specified Operand.
void AddFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
};
} // End llvm namespace