intel/compiler/fs: Don't generate integer DWord multiply on Gen11
Like CHV et al., Gen11 does not support 32x32 -> 32/64-bit integer multiplies. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -382,6 +382,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
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.has_llc = true, \
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.has_sample_with_hiz = false, \
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.has_pln = true, \
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.has_integer_dword_mul = true, \
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.has_64bit_types = true, \
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.supports_simd16_3src = true, \
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.has_surface_tile_offset = true, \
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@ -464,6 +465,7 @@ static const struct gen_device_info gen_device_info_bdw_gt3 = {
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static const struct gen_device_info gen_device_info_chv = {
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GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
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.has_llc = false,
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.has_integer_dword_mul = false,
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.num_slices = 1,
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.num_subslices = { 2, },
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.num_thread_per_eu = 7,
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@ -514,6 +516,7 @@ static const struct gen_device_info gen_device_info_chv = {
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#define GEN9_LP_FEATURES \
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GEN8_FEATURES, \
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GEN9_HW_INFO, \
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.has_integer_dword_mul = false, \
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.gt = 1, \
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.has_llc = false, \
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.has_sample_with_hiz = true, \
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@ -818,6 +821,7 @@ static const struct gen_device_info gen_device_info_cnl_5x8 = {
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GEN8_FEATURES, \
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GEN11_HW_INFO, \
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.has_64bit_types = false, \
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.has_integer_dword_mul = false, \
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.gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
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.num_subslices = _subslices
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@ -60,6 +60,7 @@ struct gen_device_info
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bool has_pln;
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bool has_64bit_types;
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bool has_integer_dword_mul;
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bool has_compr4;
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bool has_surface_tile_offset;
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bool supports_simd16_3src;
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@ -3549,11 +3549,7 @@ fs_visitor::lower_integer_multiplication()
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inst->dst.type != BRW_REGISTER_TYPE_UD))
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continue;
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/* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
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* operation directly, but CHV/BXT cannot.
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*/
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if (devinfo->gen >= 8 &&
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!devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo))
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if (devinfo->has_integer_dword_mul)
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continue;
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if (inst->src[1].file == IMM &&
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