radv: refactor physical device properties
Based on ANV. This removes a bunch of duplicated code for properties.
Fixes: 1b8d99e288 ("radv: bump conformance version to 1.2.0.0")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
5b9fe18485
commit
3a3b16a395
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@ -1427,6 +1427,148 @@ void radv_GetPhysicalDeviceProperties(
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memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
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}
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static void
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radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
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VkPhysicalDeviceVulkan11Properties *p)
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{
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assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
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memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
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memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
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memset(p->deviceLUID, 0, VK_LUID_SIZE);
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/* The LUID is for Windows. */
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p->deviceLUIDValid = false;
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p->deviceNodeMask = 0;
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p->subgroupSize = RADV_SUBGROUP_SIZE;
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p->subgroupSupportedStages = VK_SHADER_STAGE_ALL;
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p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
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VK_SUBGROUP_FEATURE_VOTE_BIT |
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VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
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VK_SUBGROUP_FEATURE_BALLOT_BIT |
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VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
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VK_SUBGROUP_FEATURE_QUAD_BIT;
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if (pdevice->rad_info.chip_class == GFX8 ||
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pdevice->rad_info.chip_class == GFX9) {
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p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
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VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
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}
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p->subgroupQuadOperationsInAllStages = true;
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p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
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p->maxMultiviewViewCount = MAX_VIEWS;
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p->maxMultiviewInstanceIndex = INT_MAX;
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p->protectedNoFault = false;
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p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
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p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
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}
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static void
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radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
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VkPhysicalDeviceVulkan12Properties *p)
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{
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assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
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p->driverID = VK_DRIVER_ID_MESA_RADV;
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snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
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snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
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"Mesa " PACKAGE_VERSION MESA_GIT_SHA1
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" (LLVM " MESA_LLVM_VERSION_STRING ")");
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p->conformanceVersion = (VkConformanceVersion) {
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.major = 1,
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.minor = 2,
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.subminor = 0,
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.patch = 0,
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};
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/* On AMD hardware, denormals and rounding modes for fp16/fp64 are
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* controlled by the same config register.
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*/
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p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
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p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
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/* Do not allow both preserving and flushing denorms because different
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* shaders in the same pipeline can have different settings and this
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* won't work for merged shaders. To make it work, this requires LLVM
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* support for changing the register. The same logic applies for the
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* rounding modes because they are configured with the same config
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* register. TODO: we can enable a lot of these for ACO when it
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* supports all stages.
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*/
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p->shaderDenormFlushToZeroFloat32 = true;
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p->shaderDenormPreserveFloat32 = false;
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p->shaderRoundingModeRTEFloat32 = true;
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p->shaderRoundingModeRTZFloat32 = false;
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p->shaderSignedZeroInfNanPreserveFloat32 = true;
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p->shaderDenormFlushToZeroFloat16 = false;
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p->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
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p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
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p->shaderRoundingModeRTZFloat16 = false;
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p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
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p->shaderDenormFlushToZeroFloat64 = false;
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p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
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p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
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p->shaderRoundingModeRTZFloat64 = false;
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p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
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p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
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p->shaderUniformBufferArrayNonUniformIndexingNative = false;
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p->shaderSampledImageArrayNonUniformIndexingNative = false;
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p->shaderStorageBufferArrayNonUniformIndexingNative = false;
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p->shaderStorageImageArrayNonUniformIndexingNative = false;
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p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
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p->robustBufferAccessUpdateAfterBind = false;
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p->quadDivergentImplicitLod = false;
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size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
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MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
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(32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
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32 /* storage buffer, 32 due to potential space wasted on alignment */ +
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32 /* sampler, largest when combined with image */ +
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64 /* sampled image */ +
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64 /* storage image */);
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p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
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p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
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p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
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p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
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p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
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p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
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p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
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p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
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p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
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p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
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p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
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p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
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p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
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p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
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p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
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/* We support all of the depth resolve modes */
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p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
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VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
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VK_RESOLVE_MODE_MIN_BIT_KHR |
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VK_RESOLVE_MODE_MAX_BIT_KHR;
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/* Average doesn't make sense for stencil so we don't support that */
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p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
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VK_RESOLVE_MODE_MIN_BIT_KHR |
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VK_RESOLVE_MODE_MAX_BIT_KHR;
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p->independentResolveNone = true;
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p->independentResolve = true;
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/* GFX6-8 only support single channel min/max filter. */
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p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
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p->filterMinmaxSingleComponentFormats = true;
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p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
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p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
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}
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void radv_GetPhysicalDeviceProperties2(
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VkPhysicalDevice physicalDevice,
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VkPhysicalDeviceProperties2 *pProperties)
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@ -1434,6 +1576,23 @@ void radv_GetPhysicalDeviceProperties2(
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RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
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radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
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VkPhysicalDeviceVulkan11Properties core_1_1 = {
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.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
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};
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radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
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VkPhysicalDeviceVulkan12Properties core_1_2 = {
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.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
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};
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radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
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#define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
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memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
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sizeof(core_##major##_##minor.core_property))
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#define CORE_PROPERTY(major, minor, property) \
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CORE_RENAMED_PROPERTY(major, minor, property, property)
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vk_foreach_struct(ext, pProperties->pNext) {
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switch (ext->sType) {
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
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@ -1444,21 +1603,22 @@ void radv_GetPhysicalDeviceProperties2(
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
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VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
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memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
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memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
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properties->deviceLUIDValid = false;
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CORE_PROPERTY(1, 1, deviceUUID);
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CORE_PROPERTY(1, 1, driverUUID);
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CORE_PROPERTY(1, 1, deviceLUID);
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CORE_PROPERTY(1, 1, deviceLUIDValid);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
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VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
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properties->maxMultiviewViewCount = MAX_VIEWS;
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properties->maxMultiviewInstanceIndex = INT_MAX;
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CORE_PROPERTY(1, 1, maxMultiviewViewCount);
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CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
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VkPhysicalDevicePointClippingProperties *properties =
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(VkPhysicalDevicePointClippingProperties*)ext;
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properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
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CORE_PROPERTY(1, 1, pointClippingBehavior);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
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@ -1476,37 +1636,27 @@ void radv_GetPhysicalDeviceProperties2(
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
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VkPhysicalDeviceSubgroupProperties *properties =
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(VkPhysicalDeviceSubgroupProperties*)ext;
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properties->subgroupSize = RADV_SUBGROUP_SIZE;
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properties->supportedStages = VK_SHADER_STAGE_ALL;
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properties->supportedOperations =
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VK_SUBGROUP_FEATURE_BASIC_BIT |
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VK_SUBGROUP_FEATURE_VOTE_BIT |
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VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
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VK_SUBGROUP_FEATURE_BALLOT_BIT |
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VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
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VK_SUBGROUP_FEATURE_QUAD_BIT;
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if (pdevice->rad_info.chip_class == GFX8 ||
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pdevice->rad_info.chip_class == GFX9) {
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properties->supportedOperations |=
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VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
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VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
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}
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properties->quadOperationsInAllStages = true;
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CORE_PROPERTY(1, 1, subgroupSize);
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CORE_RENAMED_PROPERTY(1, 1, supportedStages,
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subgroupSupportedStages);
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CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
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subgroupSupportedOperations);
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CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
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subgroupQuadOperationsInAllStages);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
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VkPhysicalDeviceMaintenance3Properties *properties =
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(VkPhysicalDeviceMaintenance3Properties*)ext;
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properties->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
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properties->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
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CORE_PROPERTY(1, 1, maxPerSetDescriptors);
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CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
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VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
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(VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
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/* GFX6-8 only support single channel min/max filter. */
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properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
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properties->filterMinmaxSingleComponentFormats = true;
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CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
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CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
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@ -1566,37 +1716,35 @@ void radv_GetPhysicalDeviceProperties2(
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
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VkPhysicalDeviceDescriptorIndexingProperties *properties =
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(VkPhysicalDeviceDescriptorIndexingProperties*)ext;
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properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
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properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
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properties->shaderSampledImageArrayNonUniformIndexingNative = false;
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properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
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properties->shaderStorageImageArrayNonUniformIndexingNative = false;
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properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
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properties->robustBufferAccessUpdateAfterBind = false;
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properties->quadDivergentImplicitLod = false;
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size_t max_descriptor_set_size = radv_max_descriptor_set_size();
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properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
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properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
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properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
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properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
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properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
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properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
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properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
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properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
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properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
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properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
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properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
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properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
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properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
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properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
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properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
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CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
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CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
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CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
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CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
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CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
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CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
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CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
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CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
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CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
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CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
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CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
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CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
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CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
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CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
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CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
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CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
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VkPhysicalDeviceProtectedMemoryProperties *properties =
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(VkPhysicalDeviceProtectedMemoryProperties *)ext;
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properties->protectedNoFault = false;
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CORE_PROPERTY(1, 1, protectedNoFault);
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
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@ -1623,21 +1771,12 @@ void radv_GetPhysicalDeviceProperties2(
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
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VkPhysicalDeviceDriverProperties *driver_props =
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VkPhysicalDeviceDriverProperties *properties =
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(VkPhysicalDeviceDriverProperties *) ext;
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driver_props->driverID = VK_DRIVER_ID_MESA_RADV;
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snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
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snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
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"Mesa " PACKAGE_VERSION MESA_GIT_SHA1
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" (LLVM " MESA_LLVM_VERSION_STRING ")");
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driver_props->conformanceVersion = (VkConformanceVersion) {
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.major = 1,
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.minor = 2,
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.subminor = 0,
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.patch = 0,
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};
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CORE_PROPERTY(1, 2, driverID);
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CORE_PROPERTY(1, 2, driverName);
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CORE_PROPERTY(1, 2, driverInfo);
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CORE_PROPERTY(1, 2, conformanceVersion);
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break;
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}
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||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
|
||||
|
|
@ -1682,22 +1821,10 @@ void radv_GetPhysicalDeviceProperties2(
|
|||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
|
||||
VkPhysicalDeviceDepthStencilResolveProperties *properties =
|
||||
(VkPhysicalDeviceDepthStencilResolveProperties *)ext;
|
||||
|
||||
/* We support all of the depth resolve modes */
|
||||
properties->supportedDepthResolveModes =
|
||||
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
|
||||
VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MIN_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MAX_BIT_KHR;
|
||||
|
||||
/* Average doesn't make sense for stencil so we don't support that */
|
||||
properties->supportedStencilResolveModes =
|
||||
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MIN_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MAX_BIT_KHR;
|
||||
|
||||
properties->independentResolveNone = true;
|
||||
properties->independentResolve = true;
|
||||
CORE_PROPERTY(1, 2, supportedDepthResolveModes);
|
||||
CORE_PROPERTY(1, 2, supportedStencilResolveModes);
|
||||
CORE_PROPERTY(1, 2, independentResolveNone);
|
||||
CORE_PROPERTY(1, 2, independentResolve);
|
||||
break;
|
||||
}
|
||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
|
||||
|
|
@ -1712,47 +1839,29 @@ void radv_GetPhysicalDeviceProperties2(
|
|||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
|
||||
VkPhysicalDeviceFloatControlsProperties *properties =
|
||||
(VkPhysicalDeviceFloatControlsProperties *)ext;
|
||||
|
||||
/* On AMD hardware, denormals and rounding modes for
|
||||
* fp16/fp64 are controlled by the same config
|
||||
* register.
|
||||
*/
|
||||
properties->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY;
|
||||
properties->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY;
|
||||
|
||||
/* Do not allow both preserving and flushing denorms
|
||||
* because different shaders in the same pipeline can
|
||||
* have different settings and this won't work for
|
||||
* merged shaders. To make it work, this requires LLVM
|
||||
* support for changing the register. The same logic
|
||||
* applies for the rounding modes because they are
|
||||
* configured with the same config register.
|
||||
* TODO: we can enable a lot of these for ACO when it
|
||||
* supports all stages
|
||||
*/
|
||||
properties->shaderDenormFlushToZeroFloat32 = true;
|
||||
properties->shaderDenormPreserveFloat32 = false;
|
||||
properties->shaderRoundingModeRTEFloat32 = true;
|
||||
properties->shaderRoundingModeRTZFloat32 = false;
|
||||
properties->shaderSignedZeroInfNanPreserveFloat32 = true;
|
||||
|
||||
properties->shaderDenormFlushToZeroFloat16 = false;
|
||||
properties->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
|
||||
properties->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
|
||||
properties->shaderRoundingModeRTZFloat16 = false;
|
||||
properties->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
|
||||
|
||||
properties->shaderDenormFlushToZeroFloat64 = false;
|
||||
properties->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
|
||||
properties->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
|
||||
properties->shaderRoundingModeRTZFloat64 = false;
|
||||
properties->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
|
||||
CORE_PROPERTY(1, 2, denormBehaviorIndependence);
|
||||
CORE_PROPERTY(1, 2, roundingModeIndependence);
|
||||
CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
|
||||
CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
|
||||
CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
|
||||
CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
|
||||
CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
|
||||
CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
|
||||
CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
|
||||
CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
|
||||
CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
|
||||
CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
|
||||
CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
|
||||
CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
|
||||
CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
|
||||
CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
|
||||
CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
|
||||
break;
|
||||
}
|
||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
|
||||
VkPhysicalDeviceTimelineSemaphoreProperties *props =
|
||||
VkPhysicalDeviceTimelineSemaphoreProperties *properties =
|
||||
(VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
|
||||
props->maxTimelineSemaphoreValueDifference = UINT64_MAX;
|
||||
CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
|
||||
break;
|
||||
}
|
||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
|
||||
|
|
@ -1770,138 +1879,12 @@ void radv_GetPhysicalDeviceProperties2(
|
|||
}
|
||||
break;
|
||||
}
|
||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES: {
|
||||
VkPhysicalDeviceVulkan11Properties *props =
|
||||
(VkPhysicalDeviceVulkan11Properties *)ext;
|
||||
|
||||
memcpy(props->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
|
||||
memcpy(props->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
|
||||
memset(props->deviceLUID, 0, VK_LUID_SIZE);
|
||||
/* The LUID is for Windows. */
|
||||
props->deviceLUIDValid = false;
|
||||
props->deviceNodeMask = 0;
|
||||
{
|
||||
props->subgroupSize = RADV_SUBGROUP_SIZE;
|
||||
props->subgroupSupportedStages = VK_SHADER_STAGE_ALL;
|
||||
props->subgroupSupportedOperations =
|
||||
VK_SUBGROUP_FEATURE_BASIC_BIT |
|
||||
VK_SUBGROUP_FEATURE_VOTE_BIT |
|
||||
VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
|
||||
VK_SUBGROUP_FEATURE_BALLOT_BIT |
|
||||
VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
|
||||
VK_SUBGROUP_FEATURE_QUAD_BIT;
|
||||
if (pdevice->rad_info.chip_class == GFX8 ||
|
||||
pdevice->rad_info.chip_class == GFX9) {
|
||||
props->subgroupSupportedOperations |=
|
||||
VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
|
||||
VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
|
||||
}
|
||||
props->subgroupQuadOperationsInAllStages = true;
|
||||
}
|
||||
props->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
|
||||
props->maxMultiviewViewCount = MAX_VIEWS;
|
||||
props->maxMultiviewInstanceIndex = INT_MAX;
|
||||
props->protectedNoFault = false;
|
||||
props->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
|
||||
props->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
|
||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
|
||||
radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
|
||||
break;
|
||||
}
|
||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES: {
|
||||
VkPhysicalDeviceVulkan12Properties *props =
|
||||
(VkPhysicalDeviceVulkan12Properties *)ext;
|
||||
|
||||
{
|
||||
props->driverID = VK_DRIVER_ID_MESA_RADV;
|
||||
snprintf(props->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
|
||||
snprintf(props->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
|
||||
"Mesa " PACKAGE_VERSION MESA_GIT_SHA1
|
||||
" (LLVM " MESA_LLVM_VERSION_STRING ")");
|
||||
|
||||
props->conformanceVersion = (VkConformanceVersion) {
|
||||
.major = 1,
|
||||
.minor = 1,
|
||||
.subminor = 2,
|
||||
.patch = 0,
|
||||
};
|
||||
}
|
||||
|
||||
props->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
|
||||
props->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
|
||||
|
||||
props->shaderDenormFlushToZeroFloat32 = true;
|
||||
props->shaderDenormPreserveFloat32 = false;
|
||||
props->shaderRoundingModeRTEFloat32 = true;
|
||||
props->shaderRoundingModeRTZFloat32 = false;
|
||||
props->shaderSignedZeroInfNanPreserveFloat32 = true;
|
||||
|
||||
props->shaderDenormFlushToZeroFloat16 = false;
|
||||
props->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
|
||||
props->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
|
||||
props->shaderRoundingModeRTZFloat16 = false;
|
||||
props->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
|
||||
|
||||
props->shaderDenormFlushToZeroFloat64 = false;
|
||||
props->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
|
||||
props->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
|
||||
props->shaderRoundingModeRTZFloat64 = false;
|
||||
props->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
|
||||
|
||||
props->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
|
||||
props->shaderUniformBufferArrayNonUniformIndexingNative = false;
|
||||
props->shaderSampledImageArrayNonUniformIndexingNative = false;
|
||||
props->shaderStorageBufferArrayNonUniformIndexingNative = false;
|
||||
props->shaderStorageImageArrayNonUniformIndexingNative = false;
|
||||
props->shaderInputAttachmentArrayNonUniformIndexingNative = false;
|
||||
props->robustBufferAccessUpdateAfterBind = false;
|
||||
props->quadDivergentImplicitLod = false;
|
||||
|
||||
size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
|
||||
MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
|
||||
(32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
|
||||
32 /* storage buffer, 32 due to potential space wasted on alignment */ +
|
||||
32 /* sampler, largest when combined with image */ +
|
||||
64 /* sampled image */ +
|
||||
64 /* storage image */);
|
||||
props->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
|
||||
props->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
|
||||
props->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
|
||||
props->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
|
||||
props->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
|
||||
props->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
|
||||
props->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
|
||||
props->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
|
||||
props->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
|
||||
props->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
|
||||
props->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
|
||||
props->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
|
||||
props->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
|
||||
props->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
|
||||
props->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
|
||||
|
||||
/* We support all of the depth resolve modes */
|
||||
props->supportedDepthResolveModes =
|
||||
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
|
||||
VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MIN_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MAX_BIT_KHR;
|
||||
|
||||
/* Average doesn't make sense for stencil so we don't support that */
|
||||
props->supportedStencilResolveModes =
|
||||
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MIN_BIT_KHR |
|
||||
VK_RESOLVE_MODE_MAX_BIT_KHR;
|
||||
|
||||
props->independentResolveNone = true;
|
||||
props->independentResolve = true;
|
||||
|
||||
props->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
|
||||
props->filterMinmaxSingleComponentFormats = true;
|
||||
|
||||
props->maxTimelineSemaphoreValueDifference = UINT64_MAX;
|
||||
|
||||
props->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
|
||||
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
|
||||
radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue