broadcom/vc5: Port the simulator to support V3D 4.1
This required moving the register accesses to a separate v3dx file, since the register definitions for each V3D version collide. It seems that initializing the v3d_hw from a file dictating 3.3 (v3d_simulator_wrapper.cpp) is safe, though.
This commit is contained in:
parent
c81cc767e4
commit
39ce1ab7ba
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@ -26,5 +26,6 @@ C_SOURCES := \
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$()
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VC5_PER_VERSION_SOURCES = \
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v3dx_simulator.c \
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vc5_rcl.c \
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$()
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@ -46,6 +46,7 @@ files_libvc5 = files(
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)
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files_per_version = files(
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'v3dx_simulator.c',
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'vc5_rcl.c',
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)
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@ -26,4 +26,12 @@
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* be included from vc5_context.h.
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*/
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struct v3d_hw;
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void v3dX(emit_rcl)(struct vc5_job *job);
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void v3dX(simulator_init_regs)(struct v3d_hw *v3d);
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int v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
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struct drm_vc5_get_param *args);
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void v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_vc5_submit_cl *submit,
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uint32_t gmp_ofs);
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@ -0,0 +1,179 @@
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/*
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* Copyright © 2014-2017 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/**
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* @file vc5_simulator_hw.c
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*
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* Implements the actual HW interaction betweeh the GL driver's VC5 simulator and the simulator.
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*
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* The register headers between V3D versions will have conflicting defines, so
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* all register interactions appear in this file and are compiled per V3D version
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* we support.
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*/
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#ifdef USE_VC5_SIMULATOR
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#include "vc5_screen.h"
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#include "vc5_context.h"
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#include "vc5_simulator_wrapper.h"
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#define HW_REGISTER_RO(x) (x)
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#define HW_REGISTER_RW(x) (x)
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#if V3D_VERSION >= 41
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#include "libs/core/v3d/registers/4.1.34.0/v3d.h"
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#else
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#include "libs/core/v3d/registers/3.3.0.0/v3d.h"
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#endif
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#define V3D_WRITE(reg, val) v3d_hw_write_reg(v3d, reg, val)
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#define V3D_READ(reg) v3d_hw_read_reg(v3d, reg)
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static void
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vc5_flush_l3(struct v3d_hw *v3d)
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{
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if (!v3d_hw_has_gca(v3d))
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return;
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#if V3D_VERSION < 40
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uint32_t gca_ctrl = V3D_READ(V3D_GCA_CACHE_CTRL);
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V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH_SET);
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V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH_SET);
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#endif
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}
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/* Invalidates the L2 cache. This is a read-only cache. */
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static void
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vc5_flush_l2(struct v3d_hw *v3d)
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{
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V3D_WRITE(V3D_CTL_0_L2CACTL,
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V3D_CTL_0_L2CACTL_L2CCLR_SET |
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V3D_CTL_0_L2CACTL_L2CENA_SET);
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}
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/* Invalidates texture L2 cachelines */
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static void
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vc5_flush_l2t(struct v3d_hw *v3d)
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{
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V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
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V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
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V3D_WRITE(V3D_CTL_0_L2TCACTL,
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V3D_CTL_0_L2TCACTL_L2TFLS_SET |
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(0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
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}
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/* Invalidates the slice caches. These are read-only caches. */
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static void
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vc5_flush_slices(struct v3d_hw *v3d)
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{
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V3D_WRITE(V3D_CTL_0_SLCACTL, ~0);
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}
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static void
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vc5_flush_caches(struct v3d_hw *v3d)
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{
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vc5_flush_l3(v3d);
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vc5_flush_l2(v3d);
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vc5_flush_l2t(v3d);
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vc5_flush_slices(v3d);
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}
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int
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v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
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struct drm_vc5_get_param *args)
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{
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static const uint32_t reg_map[] = {
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[DRM_VC5_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
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[DRM_VC5_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
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[DRM_VC5_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
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[DRM_VC5_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
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[DRM_VC5_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0,
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[DRM_VC5_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1,
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[DRM_VC5_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2,
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};
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if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {
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args->value = V3D_READ(reg_map[args->param]);
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return 0;
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}
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fprintf(stderr, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
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(long long)args->value);
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abort();
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}
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void
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v3dX(simulator_init_regs)(struct v3d_hw *v3d)
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{
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#if V3D_VERSION == 33
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/* Set OVRTMUOUT to match kernel behavior.
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*
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* This means that the texture sampler uniform configuration's tmu
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* output type field is used, instead of using the hardware default
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* behavior based on the texture type. If you want the default
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* behavior, you can still put "2" in the indirect texture state's
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* output_type field.
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*/
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V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET);
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#endif
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}
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void
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v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_vc5_submit_cl *submit,
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uint32_t gmp_ofs)
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{
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/* Completely reset the GMP. */
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V3D_WRITE(V3D_GMP_0_CFG,
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V3D_GMP_0_CFG_PROTENABLE_SET);
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V3D_WRITE(V3D_GMP_0_TABLE_ADDR, gmp_ofs);
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V3D_WRITE(V3D_GMP_0_CLEAR_LOAD, ~0);
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while (V3D_READ(V3D_GMP_0_STATUS) &
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V3D_GMP_0_STATUS_CFG_BUSY_SET) {
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;
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}
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vc5_flush_caches(v3d);
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V3D_WRITE(V3D_CLE_0_CT0QBA, submit->bcl_start);
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V3D_WRITE(V3D_CLE_0_CT0QEA, submit->bcl_end);
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/* Wait for bin to complete before firing render, as it seems the
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* simulator doesn't implement the semaphores.
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*/
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while (V3D_READ(V3D_CLE_0_CT0CA) !=
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V3D_READ(V3D_CLE_0_CT0EA)) {
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v3d_hw_tick(v3d);
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}
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V3D_WRITE(V3D_CLE_0_CT1QBA, submit->rcl_start);
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V3D_WRITE(V3D_CLE_0_CT1QEA, submit->rcl_end);
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while (V3D_READ(V3D_CLE_0_CT1CA) !=
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V3D_READ(V3D_CLE_0_CT1EA) ||
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V3D_READ(V3D_CLE_1_CT1CA) !=
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V3D_READ(V3D_CLE_1_CT1EA)) {
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v3d_hw_tick(v3d);
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}
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}
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#endif /* USE_VC5_SIMULATOR */
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@ -452,8 +452,6 @@ void vc5_program_fini(struct pipe_context *pctx);
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void vc5_query_init(struct pipe_context *pctx);
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void vc5_simulator_init(struct vc5_screen *screen);
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void vc5_simulator_init(struct vc5_screen *screen);
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void vc5_simulator_destroy(struct vc5_screen *screen);
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void vc5_simulator_destroy(struct vc5_screen *screen);
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int vc5_simulator_flush(struct vc5_context *vc5,
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struct drm_vc5_submit_cl *args,
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void
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vc5_job_submit(struct vc5_context *vc5, struct vc5_job *job)
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{
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MAYBE_UNUSED struct vc5_screen *screen = vc5->screen;
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if (!job->needs_flush)
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goto done;
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@ -56,10 +56,6 @@
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#include "util/u_mm.h"
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#include "vc5_simulator_wrapper.h"
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#define HW_REGISTER_RO(x) (x)
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#define HW_REGISTER_RW(x) (x)
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#include "libs/core/v3d/registers/3.3.0.0/v3d.h"
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#include "vc5_screen.h"
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#include "vc5_context.h"
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mtx_t mutex;
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struct v3d_hw *v3d;
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int ver;
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/* Base virtual address of the heap. */
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void *mem;
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}
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#endif
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#define V3D_WRITE(reg, val) v3d_hw_write_reg(sim_state.v3d, reg, val)
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#define V3D_READ(reg) v3d_hw_read_reg(sim_state.v3d, reg)
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static void
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vc5_flush_l3(void)
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{
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if (!v3d_hw_has_gca(sim_state.v3d))
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return;
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uint32_t gca_ctrl = V3D_READ(V3D_GCA_CACHE_CTRL);
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V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH_SET);
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V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH_SET);
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}
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/* Invalidates the L2 cache. This is a read-only cache. */
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static void
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vc5_flush_l2(void)
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{
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V3D_WRITE(V3D_CTL_0_L2CACTL,
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V3D_CTL_0_L2CACTL_L2CCLR_SET |
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V3D_CTL_0_L2CACTL_L2CENA_SET);
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}
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/* Invalidates texture L2 cachelines */
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static void
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vc5_flush_l2t(void)
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{
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V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
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V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
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V3D_WRITE(V3D_CTL_0_L2TCACTL,
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V3D_CTL_0_L2TCACTL_L2TFLS_SET |
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(0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
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}
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/* Invalidates the slice caches. These are read-only caches. */
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static void
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vc5_flush_slices(void)
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{
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V3D_WRITE(V3D_CTL_0_SLCACTL, ~0);
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}
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static void
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vc5_flush_caches(void)
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{
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vc5_flush_l3();
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vc5_flush_l2();
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vc5_flush_l2t();
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vc5_flush_slices();
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}
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int
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vc5_simulator_flush(struct vc5_context *vc5,
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struct drm_vc5_submit_cl *submit, struct vc5_job *job)
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@ -447,38 +393,10 @@ vc5_simulator_flush(struct vc5_context *vc5,
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//vc5_dump_to_file(&exec);
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/* Completely reset the GMP. */
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v3d_hw_write_reg(sim_state.v3d, V3D_GMP_0_CFG,
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V3D_GMP_0_CFG_PROTENABLE_SET);
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v3d_hw_write_reg(sim_state.v3d, V3D_GMP_0_TABLE_ADDR, file->gmp->ofs);
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v3d_hw_write_reg(sim_state.v3d, V3D_GMP_0_CLEAR_LOAD, ~0);
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while (v3d_hw_read_reg(sim_state.v3d, V3D_GMP_0_STATUS) &
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V3D_GMP_0_STATUS_CFG_BUSY_SET) {
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;
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}
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vc5_flush_caches();
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v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT0QBA, submit->bcl_start);
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v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT0QEA, submit->bcl_end);
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/* Wait for bin to complete before firing render, as it seems the
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* simulator doesn't implement the semaphores.
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*/
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while (v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT0CA) !=
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v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT0EA)) {
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v3d_hw_tick(sim_state.v3d);
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}
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v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT1QBA, submit->rcl_start);
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v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT1QEA, submit->rcl_end);
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while (v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT1CA) !=
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v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT1EA) ||
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v3d_hw_read_reg(sim_state.v3d, V3D_CLE_1_CT1CA) !=
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v3d_hw_read_reg(sim_state.v3d, V3D_CLE_1_CT1EA)) {
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v3d_hw_tick(sim_state.v3d);
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}
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if (sim_state.ver >= 41)
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v3d41_simulator_flush(sim_state.v3d, submit, file->gmp->ofs);
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else
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v3d33_simulator_flush(sim_state.v3d, submit, file->gmp->ofs);
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ret = vc5_simulator_unpin_bos(fd, job);
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if (ret)
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@ -607,25 +525,10 @@ vc5_simulator_gem_close_ioctl(int fd, struct drm_gem_close *args)
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static int
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vc5_simulator_get_param_ioctl(int fd, struct drm_vc5_get_param *args)
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{
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static const uint32_t reg_map[] = {
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[DRM_VC5_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
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[DRM_VC5_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
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[DRM_VC5_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
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[DRM_VC5_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
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[DRM_VC5_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0,
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[DRM_VC5_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1,
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[DRM_VC5_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2,
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};
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if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {
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args->value = v3d_hw_read_reg(sim_state.v3d,
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reg_map[args->param]);
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return 0;
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}
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fprintf(stderr, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
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(long long)args->value);
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abort();
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if (sim_state.ver >= 41)
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return v3d41_simulator_get_param_ioctl(sim_state.v3d, args);
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else
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return v3d33_simulator_get_param_ioctl(sim_state.v3d, args);
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}
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int
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@ -662,21 +565,7 @@ vc5_simulator_ioctl(int fd, unsigned long request, void *args)
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}
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static void
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vc5_simulator_init_regs(void)
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{
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/* Set OVRTMUOUT to match kernel behavior.
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*
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* This means that the texture sampler uniform configuration's tmu
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* output type field is used, instead of using the hardware default
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* behavior based on the texture type. If you want the default
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* behavior, you can still put "2" in the indirect texture state's
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* output_type field.
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*/
|
||||
V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET);
|
||||
}
|
||||
|
||||
static void
|
||||
vc5_simulator_init_global(void)
|
||||
vc5_simulator_init_global(const struct v3d_device_info *devinfo)
|
||||
{
|
||||
mtx_lock(&sim_state.mutex);
|
||||
if (sim_state.refcount++) {
|
||||
|
@ -698,6 +587,8 @@ vc5_simulator_init_global(void)
|
|||
struct mem_block *b = u_mmAllocMem(sim_state.heap, 4096, GMP_ALIGN2, 0);
|
||||
memset(sim_state.mem + b->ofs - sim_state.mem_base, 0xd0, 4096);
|
||||
|
||||
sim_state.ver = v3d_hw_get_version(sim_state.v3d);
|
||||
|
||||
mtx_unlock(&sim_state.mutex);
|
||||
|
||||
sim_state.fd_map =
|
||||
|
@ -705,13 +596,16 @@ vc5_simulator_init_global(void)
|
|||
_mesa_hash_pointer,
|
||||
_mesa_key_pointer_equal);
|
||||
|
||||
vc5_simulator_init_regs();
|
||||
if (sim_state.ver >= 41)
|
||||
v3d41_simulator_init_regs(sim_state.v3d);
|
||||
else
|
||||
v3d33_simulator_init_regs(sim_state.v3d);
|
||||
}
|
||||
|
||||
void
|
||||
vc5_simulator_init(struct vc5_screen *screen)
|
||||
{
|
||||
vc5_simulator_init_global();
|
||||
vc5_simulator_init_global(&screen->devinfo);
|
||||
|
||||
screen->sim_file = rzalloc(screen, struct vc5_simulator_file);
|
||||
struct vc5_simulator_file *sim_file = screen->sim_file;
|
||||
|
|
|
@ -76,6 +76,13 @@ void v3d_hw_tick(struct v3d_hw *hw)
|
|||
return hw->tick();
|
||||
}
|
||||
|
||||
int v3d_hw_get_version(struct v3d_hw *hw)
|
||||
{
|
||||
const V3D_HUB_IDENT_T *ident = hw->get_hub_ident();
|
||||
|
||||
return ident->tech_version * 10 + ident->revision;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif /* USE_VC5_SIMULATOR */
|
||||
|
|
|
@ -37,6 +37,7 @@ bool v3d_hw_has_gca(struct v3d_hw *hw);
|
|||
uint32_t v3d_hw_read_reg(struct v3d_hw *hw, uint32_t reg);
|
||||
void v3d_hw_write_reg(struct v3d_hw *hw, uint32_t reg, uint32_t val);
|
||||
void v3d_hw_tick(struct v3d_hw *hw);
|
||||
int v3d_hw_get_version(struct v3d_hw *hw);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue