panfrost/midgard: Route new blending intrinsics
To prepare for the new nir_lower_blend pass, we wire up the intrinsics for tilebuffer reads and constant colour loading. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
a1885b2a35
commit
39104221e1
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@ -435,7 +435,6 @@ typedef struct compiler_context {
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bool is_blend;
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/* Tracking for blend constant patching */
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int blend_constant_number;
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int blend_constant_offset;
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/* Current NIR function */
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@ -671,11 +670,6 @@ attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constant
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{
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ins->has_constants = true;
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memcpy(&ins->constants, constants, 16);
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/* If this is the special blend constant, mark this instruction */
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if (ctx->is_blend && ctx->blend_constant_number == name)
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ins->has_blend_constant = true;
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}
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static int
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@ -1521,6 +1515,79 @@ emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
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emit_uniform_read(ctx, dest, uniform, NULL);
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}
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/* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
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* using scalar ops functional on earlier Midgard generations. Newer Midgard
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* generations have faster vectorized reads. This operation is for blend
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* shaders in particular; reading the tilebuffer from the fragment shader
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* remains an open problem. */
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static void
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emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
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{
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midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
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ins.load_store.swizzle = 0; /* xxxx */
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/* Read each component sequentially */
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for (unsigned c = 0; c < 4; ++c) {
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ins.load_store.mask = (1 << c);
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ins.load_store.unknown = c;
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emit_mir_instruction(ctx, ins);
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}
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/* vadd.u2f hr2, zext(hr2), #0 */
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midgard_vector_alu_src alu_src = blank_alu_src;
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alu_src.mod = midgard_int_zero_extend;
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alu_src.half = true;
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midgard_instruction u2f = {
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.type = TAG_ALU_4,
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.ssa_args = {
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.src0 = reg,
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.src1 = SSA_UNUSED_0,
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.dest = reg,
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.inline_constant = true
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},
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.alu = {
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.op = midgard_alu_op_u2f,
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.reg_mode = midgard_reg_mode_16,
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.dest_override = midgard_dest_override_none,
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.mask = 0xF,
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.src1 = vector_alu_srco_unsigned(alu_src),
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.src2 = vector_alu_srco_unsigned(blank_alu_src),
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}
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};
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emit_mir_instruction(ctx, u2f);
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/* vmul.fmul.sat r1, hr2, #0.00392151 */
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alu_src.mod = 0;
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midgard_instruction fmul = {
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.type = TAG_ALU_4,
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.inline_constant = _mesa_float_to_half(1.0 / 255.0),
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.ssa_args = {
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.src0 = reg,
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.dest = reg,
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.src1 = SSA_UNUSED_0,
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.inline_constant = true
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},
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.alu = {
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.op = midgard_alu_op_fmul,
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.reg_mode = midgard_reg_mode_32,
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.dest_override = midgard_dest_override_none,
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.outmod = midgard_outmod_sat,
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.mask = 0xFF,
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.src1 = vector_alu_srco_unsigned(alu_src),
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.src2 = vector_alu_srco_unsigned(blank_alu_src),
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}
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};
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emit_mir_instruction(ctx, fmul);
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}
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static void
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emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
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{
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@ -1582,106 +1649,13 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
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ins.load_store.unknown = 0x79e; /* xxx: what is this? */
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}
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emit_mir_instruction(ctx, ins);
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} else if (ctx->is_blend && instr->intrinsic == nir_intrinsic_load_uniform) {
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/* Constant encoded as a pinned constant */
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midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
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ins.has_constants = true;
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ins.has_blend_constant = true;
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emit_mir_instruction(ctx, ins);
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} else if (ctx->is_blend) {
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/* For blend shaders, a load might be
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* translated various ways depending on what
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* we're loading. Figure out how this is used */
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/* For blend shaders, load the input color, which is
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* preloaded to r0 */
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nir_variable *out = NULL;
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nir_foreach_variable(var, &ctx->nir->inputs) {
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int drvloc = var->data.driver_location;
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if (nir_intrinsic_base(instr) == drvloc) {
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out = var;
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break;
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}
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}
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assert(out);
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if (out->data.location == VARYING_SLOT_COL0) {
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/* Source color preloaded to r0 */
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midgard_pin_output(ctx, reg, 0);
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} else if (out->data.location == VARYING_SLOT_COL1) {
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/* Destination color must be read from framebuffer */
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midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
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ins.load_store.swizzle = 0; /* xxxx */
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/* Read each component sequentially */
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for (int c = 0; c < 4; ++c) {
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ins.load_store.mask = (1 << c);
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ins.load_store.unknown = c;
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emit_mir_instruction(ctx, ins);
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}
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/* vadd.u2f hr2, zext(hr2), #0 */
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midgard_vector_alu_src alu_src = blank_alu_src;
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alu_src.mod = midgard_int_zero_extend;
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alu_src.half = true;
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midgard_instruction u2f = {
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.type = TAG_ALU_4,
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.ssa_args = {
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.src0 = reg,
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.src1 = SSA_UNUSED_0,
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.dest = reg,
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.inline_constant = true
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},
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.alu = {
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.op = midgard_alu_op_u2f,
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.reg_mode = midgard_reg_mode_16,
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.dest_override = midgard_dest_override_none,
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.mask = 0xF,
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.src1 = vector_alu_srco_unsigned(alu_src),
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.src2 = vector_alu_srco_unsigned(blank_alu_src),
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}
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};
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emit_mir_instruction(ctx, u2f);
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/* vmul.fmul.sat r1, hr2, #0.00392151 */
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alu_src.mod = 0;
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midgard_instruction fmul = {
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.type = TAG_ALU_4,
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.inline_constant = _mesa_float_to_half(1.0 / 255.0),
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.ssa_args = {
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.src0 = reg,
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.dest = reg,
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.src1 = SSA_UNUSED_0,
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.inline_constant = true
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},
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.alu = {
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.op = midgard_alu_op_fmul,
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.reg_mode = midgard_reg_mode_32,
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.dest_override = midgard_dest_override_none,
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.outmod = midgard_outmod_sat,
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.mask = 0xFF,
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.src1 = vector_alu_srco_unsigned(alu_src),
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.src2 = vector_alu_srco_unsigned(blank_alu_src),
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}
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};
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emit_mir_instruction(ctx, fmul);
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} else {
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DBG("Unknown input in blend shader\n");
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assert(0);
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}
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} else if (ctx->stage == MESA_SHADER_VERTEX) {
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midgard_pin_output(ctx, reg, 0);
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} else if (ctx->stage == MESA_SHADER_VERTEX) {
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midgard_instruction ins = m_ld_attr_32(reg, offset);
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ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
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ins.load_store.mask = (1 << instr->num_components) - 1;
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@ -1693,6 +1667,34 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
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break;
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case nir_intrinsic_load_output:
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assert(nir_src_is_const(instr->src[0]));
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reg = nir_dest_index(ctx, &instr->dest);
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if (ctx->is_blend) {
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/* TODO: MRT */
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emit_fb_read_blend_scalar(ctx, reg);
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} else {
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DBG("Unknown output load\n");
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assert(0);
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}
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break;
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case nir_intrinsic_load_blend_const_color_rgba: {
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assert(ctx->is_blend);
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reg = nir_dest_index(ctx, &instr->dest);
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/* Blend constants are embedded directly in the shader and
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* patched in, so we use some magic routing */
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midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
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ins.has_constants = true;
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ins.has_blend_constant = true;
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emit_mir_instruction(ctx, ins);
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break;
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}
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case nir_intrinsic_store_output:
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assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
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@ -1707,7 +1709,10 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
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* framebuffer writeout dance. TODO: Defer
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* writes */
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midgard_pin_output(ctx, reg, 0);
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midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
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emit_mir_instruction(ctx, move);
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//midgard_pin_output(ctx, reg, 0);
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/* Save the index we're writing to for later reference
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* in the epilogue */
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@ -2637,6 +2642,13 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
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if (ains->has_constants) {
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if (bundle.has_embedded_constants) {
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/* The blend constant needs to be
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* alone, since it conflicts with
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* everything by definition*/
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if (ains->has_blend_constant || bundle.has_blend_constant)
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break;
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/* ...but if there are already
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* constants but these are the
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* *same* constants, we let it
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@ -2649,8 +2661,7 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
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memcpy(bundle.constants, ains->constants, sizeof(bundle.constants));
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/* If this is a blend shader special constant, track it for patching */
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if (ains->has_blend_constant)
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bundle.has_blend_constant = true;
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bundle.has_blend_constant |= ains->has_blend_constant;
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}
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}
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