freedreno/ir3: decouple regset from gpu gen
Allow different regset's to coexist, so we can make mergedregs vs split reg file a variant property. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
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@ -1317,7 +1317,7 @@ bool ir3_postsched(struct ir3 *ir);
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bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
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/* register assignment: */
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struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
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struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs);
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int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
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/* legalize: */
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@ -60,9 +60,10 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
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compiler->dev = dev;
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compiler->gpu_id = gpu_id;
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compiler->set = ir3_ra_alloc_reg_set(compiler);
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compiler->set = ir3_ra_alloc_reg_set(compiler, false);
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if (compiler->gpu_id >= 600) {
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compiler->mergedregs_set = ir3_ra_alloc_reg_set(compiler, true);
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compiler->samgq_workaround = true;
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}
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@ -35,6 +35,7 @@ struct ir3_compiler {
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struct fd_device *dev;
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uint32_t gpu_id;
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struct ir3_ra_reg_set *set;
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struct ir3_ra_reg_set *mergedregs_set;
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uint32_t shader_count;
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/*
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@ -1488,7 +1488,8 @@ ir3_ra_pass(struct ir3_shader_variant *v, struct ir3_instruction **precolor,
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struct ir3_ra_ctx ctx = {
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.v = v,
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.ir = v->ir,
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.set = v->ir->compiler->set,
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.set = (v->ir->compiler->gpu_id >= 600) ?
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v->ir->compiler->mergedregs_set : v->ir->compiler->set,
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.scalar_pass = scalar_pass,
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};
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int ret;
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@ -105,7 +105,7 @@ setup_conflicts(struct ir3_ra_reg_set *set)
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* really just four scalar registers. Don't let that confuse you.)
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*/
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struct ir3_ra_reg_set *
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ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
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ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs)
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{
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struct ir3_ra_reg_set *set = rzalloc(compiler, struct ir3_ra_reg_set);
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unsigned ra_reg_count, reg, base;
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@ -195,7 +195,7 @@ ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
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* And finally setup conflicts. Starting a6xx, half precision regs
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* conflict w/ full precision regs (when using MERGEDREGS):
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*/
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if (compiler->gpu_id >= 600) {
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if (mergedregs) {
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for (unsigned i = 0; i < CLASS_REGS(0) / 2; i++) {
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unsigned freg = set->gpr_to_ra_reg[0][i];
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unsigned hreg0 = set->gpr_to_ra_reg[0 + HALF_OFFSET][(i * 2) + 0];
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