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freedreno/ir3: decouple regset from gpu gen 

Allow different regset's to coexist, so we can make mergedregs vs split
reg file a variant property.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
This commit is contained in:
Rob Clark 2020-06-12 20:56:48 -07:00 committed by Marge Bot
parent 47decc88c2
commit 38df3f899d
5 changed files with 8 additions and 5 deletions
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2
src/freedreno/ir3/ir3.h
View File

@ -1317,7 +1317,7 @@ bool ir3_postsched(struct ir3 *ir);
bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
/* register assignment: */
struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs);
int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
/* legalize: */

3
src/freedreno/ir3/ir3_compiler.c
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@ -60,9 +60,10 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
compiler->dev = dev;
compiler->gpu_id = gpu_id;
compiler->set = ir3_ra_alloc_reg_set(compiler);
compiler->set = ir3_ra_alloc_reg_set(compiler, false);
if (compiler->gpu_id >= 600) {
compiler->mergedregs_set = ir3_ra_alloc_reg_set(compiler, true);
compiler->samgq_workaround = true;
}

1
src/freedreno/ir3/ir3_compiler.h
View File

@ -35,6 +35,7 @@ struct ir3_compiler {
struct fd_device *dev;
uint32_t gpu_id;
struct ir3_ra_reg_set *set;
struct ir3_ra_reg_set *mergedregs_set;
uint32_t shader_count;
/*

3
src/freedreno/ir3/ir3_ra.c
View File

@ -1488,7 +1488,8 @@ ir3_ra_pass(struct ir3_shader_variant *v, struct ir3_instruction **precolor,
struct ir3_ra_ctx ctx = {
.v = v,
.ir = v->ir,
.set = v->ir->compiler->set,
.set = (v->ir->compiler->gpu_id >= 600) ?
v->ir->compiler->mergedregs_set : v->ir->compiler->set,
.scalar_pass = scalar_pass,
};
int ret;

4
src/freedreno/ir3/ir3_ra_regset.c
View File

@ -105,7 +105,7 @@ setup_conflicts(struct ir3_ra_reg_set *set)
* really just four scalar registers. Don't let that confuse you.)
*/
struct ir3_ra_reg_set *
ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs)
{
struct ir3_ra_reg_set *set = rzalloc(compiler, struct ir3_ra_reg_set);
unsigned ra_reg_count, reg, base;
@ -195,7 +195,7 @@ ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
* And finally setup conflicts. Starting a6xx, half precision regs
* conflict w/ full precision regs (when using MERGEDREGS):
*/
if (compiler->gpu_id >= 600) {
if (mergedregs) {
for (unsigned i = 0; i < CLASS_REGS(0) / 2; i++) {
unsigned freg = set->gpr_to_ra_reg[0][i];
unsigned hreg0 = set->gpr_to_ra_reg[0 + HALF_OFFSET][(i * 2) + 0];