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i965: Actually enable SIMD16 dispatch on Ivybridge. 

Commit acf82657f4 supposedly enabled
SIMD16 dispatch, but neglected to set the "16 Pixel Dispatch Enable"
bit, so nothing actually got enabled.

Furthermore, it neglected to set up the Dispatch GRF Start Register for
kernel 2, which is the SIMD16 program.

Increases performance in Nexuiz by ~15% at 800x600 (n=3).

NOTE: This is a candidate for the 7.11 branch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2012-01-07 21:57:46 -08:00
parent ed22f8ed2c
commit 37240d2132
1 changed files with 7 additions and 2 deletions
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9
src/mesa/drivers/dri/i965/gen7_wm_state.c
View File

@ -163,14 +163,19 @@ upload_ps_state(struct brw_context *brw)
if (brw->fragment_program->Base.InputsRead != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
if (brw->wm.prog_data->dispatch_width == 8)
if (brw->wm.prog_data->dispatch_width == 8) {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
else
if (brw->wm.prog_data->prog_offset_16)
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
} else {
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
}
/* BRW_NEW_CURBE_OFFSETS */
dw5 |= (brw->wm.prog_data->first_curbe_grf <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));