anv: Implement the basic form of VK_EXT_transform_feedback
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
parent
39925d60ec
commit
36ee2fd61c
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@ -653,6 +653,35 @@ void anv_CmdBindVertexBuffers(
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}
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}
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void anv_CmdBindTransformFeedbackBuffersEXT(
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VkCommandBuffer commandBuffer,
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uint32_t firstBinding,
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uint32_t bindingCount,
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const VkBuffer* pBuffers,
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const VkDeviceSize* pOffsets,
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const VkDeviceSize* pSizes)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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struct anv_xfb_binding *xfb = cmd_buffer->state.xfb_bindings;
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/* We have to defer setting up vertex buffer since we need the buffer
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* stride from the pipeline. */
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assert(firstBinding + bindingCount <= MAX_XFB_BUFFERS);
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for (uint32_t i = 0; i < bindingCount; i++) {
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if (pBuffers[i] == VK_NULL_HANDLE) {
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xfb[firstBinding + i].buffer = NULL;
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} else {
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ANV_FROM_HANDLE(anv_buffer, buffer, pBuffers[i]);
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xfb[firstBinding + i].buffer = buffer;
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xfb[firstBinding + i].offset = pOffsets[i];
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xfb[firstBinding + i].size =
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anv_buffer_get_range(buffer, pOffsets[i],
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pSizes ? pSizes[i] : VK_WHOLE_SIZE);
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}
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}
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}
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enum isl_format
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anv_isl_format_for_descriptor_type(VkDescriptorType type)
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{
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@ -970,6 +970,14 @@ void anv_GetPhysicalDeviceFeatures2(
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
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VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
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(VkPhysicalDeviceTransformFeedbackFeaturesEXT *)ext;
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features->transformFeedback = VK_TRUE;
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features->geometryStreams = VK_TRUE;
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
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VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
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(VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
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@ -1287,6 +1295,23 @@ void anv_GetPhysicalDeviceProperties2(
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
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VkPhysicalDeviceTransformFeedbackPropertiesEXT *props =
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(VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
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props->maxTransformFeedbackStreams = MAX_XFB_STREAMS;
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props->maxTransformFeedbackBuffers = MAX_XFB_BUFFERS;
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props->maxTransformFeedbackBufferSize = (1ull << 32);
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props->maxTransformFeedbackStreamDataSize = 128 * 4;
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props->maxTransformFeedbackBufferDataSize = 128 * 4;
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props->maxTransformFeedbackBufferDataStride = 2048;
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props->transformFeedbackQueries = VK_FALSE;
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props->transformFeedbackStreamsLinesTriangles = VK_FALSE;
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props->transformFeedbackRasterizationStreamSelect = VK_FALSE;
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props->transformFeedbackDraw = VK_FALSE;
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
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VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *props =
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(VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
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@ -132,7 +132,7 @@ EXTENSIONS = [
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Extension('VK_EXT_scalar_block_layout', 1, True),
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Extension('VK_EXT_shader_viewport_index_layer', 1, True),
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Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen >= 9'),
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Extension('VK_EXT_transform_feedback', 1, False),
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Extension('VK_EXT_transform_feedback', 1, True),
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Extension('VK_EXT_vertex_attribute_divisor', 3, True),
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Extension('VK_GOOGLE_decorate_string', 1, True),
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Extension('VK_GOOGLE_hlsl_functionality1', 1, True),
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@ -32,6 +32,7 @@
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#include "anv_private.h"
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#include "compiler/brw_nir.h"
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#include "anv_nir.h"
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#include "nir/nir_xfb_info.h"
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#include "spirv/nir_spirv.h"
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#include "vk_util.h"
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@ -138,6 +139,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
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.device_group = true,
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.draw_parameters = true,
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.float64 = pdevice->info.gen >= 8,
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.geometry_streams = true,
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.image_write_without_format = true,
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.int16 = pdevice->info.gen >= 8,
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.int64 = pdevice->info.gen >= 8,
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@ -155,6 +157,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
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.subgroup_shuffle = true,
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.subgroup_vote = true,
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.tessellation = true,
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.transform_feedback = pdevice->info.gen >= 8,
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.variable_pointers = true,
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},
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.ubo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
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@ -1082,6 +1085,12 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
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void *stage_ctx = ralloc_context(NULL);
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nir_xfb_info *xfb_info = NULL;
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if (s == MESA_SHADER_VERTEX ||
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s == MESA_SHADER_TESS_EVAL ||
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s == MESA_SHADER_GEOMETRY)
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xfb_info = nir_gather_xfb_info(stages[s].nir, stage_ctx);
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anv_pipeline_lower_nir(pipeline, stage_ctx, &stages[s], layout);
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const unsigned *code;
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@ -1123,7 +1132,7 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
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stages[s].nir->constant_data_size,
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&stages[s].prog_data.base,
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brw_prog_data_size(s),
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NULL, &stages[s].bind_map);
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xfb_info, &stages[s].bind_map);
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if (!bin) {
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ralloc_free(stage_ctx);
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result = vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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@ -151,6 +151,8 @@ struct gen_l3_config;
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#define ANV_HZ_FC_VAL 1.0f
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#define MAX_VBS 28
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#define MAX_XFB_BUFFERS 4
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#define MAX_XFB_STREAMS 4
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#define MAX_SETS 8
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#define MAX_RTS 8
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#define MAX_VIEWPORTS 16
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@ -1769,6 +1771,7 @@ enum anv_cmd_dirty_bits {
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ANV_CMD_DIRTY_PIPELINE = 1 << 9,
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ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
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ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
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ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12,
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};
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typedef uint32_t anv_cmd_dirty_mask_t;
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@ -1972,6 +1975,12 @@ struct anv_vertex_binding {
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VkDeviceSize offset;
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};
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struct anv_xfb_binding {
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struct anv_buffer * buffer;
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VkDeviceSize offset;
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VkDeviceSize size;
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};
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#define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
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#define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
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@ -2164,6 +2173,8 @@ struct anv_cmd_state {
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VkRect2D render_area;
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uint32_t restart_index;
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struct anv_vertex_binding vertex_bindings[MAX_VBS];
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bool xfb_enabled;
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struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
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VkShaderStageFlags push_constant_stages;
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struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
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struct anv_state binding_tables[MESA_SHADER_STAGES];
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@ -2582,6 +2593,8 @@ struct anv_pipeline {
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uint32_t instance_divisor;
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} vb[MAX_VBS];
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uint8_t xfb_used;
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bool primitive_restart;
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uint32_t topology;
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@ -2642,6 +2642,34 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.gfx.vb_dirty &= ~vb_emit;
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#if GEN_GEN >= 8
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_XFB_ENABLE) {
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/* We don't need any per-buffer dirty tracking because you're not
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* allowed to bind different XFB buffers while XFB is enabled.
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*/
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for (unsigned idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
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struct anv_xfb_binding *xfb = &cmd_buffer->state.xfb_bindings[idx];
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
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sob.SOBufferIndex = idx;
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if (cmd_buffer->state.xfb_enabled && xfb->buffer) {
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sob.SOBufferEnable = true;
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sob.MOCS = cmd_buffer->device->default_mocs,
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sob.StreamOffsetWriteEnable = false;
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sob.SurfaceBaseAddress = anv_address_add(xfb->buffer->address,
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xfb->offset);
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/* Size is in DWords - 1 */
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sob.SurfaceSize = xfb->size / 4 - 1;
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}
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}
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}
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/* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
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if (GEN_GEN >= 10)
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
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}
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#endif
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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@ -3272,6 +3300,107 @@ void genX(CmdDrawIndexedIndirectCountKHR)(
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}
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}
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void genX(CmdBeginTransformFeedbackEXT)(
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VkCommandBuffer commandBuffer,
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uint32_t firstCounterBuffer,
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uint32_t counterBufferCount,
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const VkBuffer* pCounterBuffers,
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const VkDeviceSize* pCounterBufferOffsets)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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assert(firstCounterBuffer < MAX_XFB_BUFFERS);
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assert(counterBufferCount <= MAX_XFB_BUFFERS);
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assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
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/* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
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*
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* "Ssoftware must ensure that no HW stream output operations can be in
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* process or otherwise pending at the point that the MI_LOAD/STORE
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* commands are processed. This will likely require a pipeline flush."
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*/
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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for (uint32_t idx = 0; idx < MAX_XFB_BUFFERS; idx++) {
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/* If we have a counter buffer, this is a resume so we need to load the
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* value into the streamout offset register. Otherwise, this is a begin
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* and we need to reset it to zero.
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*/
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if (pCounterBuffers &&
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idx >= firstCounterBuffer &&
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idx - firstCounterBuffer < counterBufferCount &&
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pCounterBuffers[idx - firstCounterBuffer] != VK_NULL_HANDLE) {
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uint32_t cb_idx = idx - firstCounterBuffer;
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ANV_FROM_HANDLE(anv_buffer, counter_buffer, pCounterBuffers[cb_idx]);
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uint64_t offset = pCounterBufferOffsets ?
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pCounterBufferOffsets[cb_idx] : 0;
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
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lrm.RegisterAddress = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
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lrm.MemoryAddress = anv_address_add(counter_buffer->address,
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offset);
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}
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} else {
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
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lri.RegisterOffset = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
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lri.DataDWord = 0;
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}
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}
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}
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cmd_buffer->state.xfb_enabled = true;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
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}
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void genX(CmdEndTransformFeedbackEXT)(
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VkCommandBuffer commandBuffer,
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uint32_t firstCounterBuffer,
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uint32_t counterBufferCount,
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const VkBuffer* pCounterBuffers,
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const VkDeviceSize* pCounterBufferOffsets)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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assert(firstCounterBuffer < MAX_XFB_BUFFERS);
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assert(counterBufferCount <= MAX_XFB_BUFFERS);
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assert(firstCounterBuffer + counterBufferCount <= MAX_XFB_BUFFERS);
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/* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
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*
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* "Ssoftware must ensure that no HW stream output operations can be in
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* process or otherwise pending at the point that the MI_LOAD/STORE
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* commands are processed. This will likely require a pipeline flush."
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*/
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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for (uint32_t cb_idx = 0; cb_idx < counterBufferCount; cb_idx++) {
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unsigned idx = firstCounterBuffer + cb_idx;
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/* If we have a counter buffer, this is a resume so we need to load the
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* value into the streamout offset register. Otherwise, this is a begin
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* and we need to reset it to zero.
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*/
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if (pCounterBuffers &&
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cb_idx < counterBufferCount &&
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pCounterBuffers[cb_idx] != VK_NULL_HANDLE) {
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ANV_FROM_HANDLE(anv_buffer, counter_buffer, pCounterBuffers[cb_idx]);
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uint64_t offset = pCounterBufferOffsets ?
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pCounterBufferOffsets[cb_idx] : 0;
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
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srm.MemoryAddress = anv_address_add(counter_buffer->address,
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offset);
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srm.RegisterAddress = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
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}
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}
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}
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cmd_buffer->state.xfb_enabled = false;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_XFB_ENABLE;
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}
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static VkResult
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flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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{
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@ -28,6 +28,7 @@
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#include "common/gen_l3_config.h"
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#include "common/gen_sample_positions.h"
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#include "nir/nir_xfb_info.h"
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#include "vk_util.h"
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#include "vk_format_info.h"
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@ -1127,9 +1128,130 @@ static void
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emit_3dstate_streamout(struct anv_pipeline *pipeline,
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const VkPipelineRasterizationStateCreateInfo *rs_info)
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{
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#if GEN_GEN >= 8
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const struct brw_vue_prog_data *prog_data =
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anv_pipeline_get_last_vue_prog_data(pipeline);
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const struct brw_vue_map *vue_map = &prog_data->vue_map;
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#endif
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nir_xfb_info *xfb_info;
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if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
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xfb_info = pipeline->shaders[MESA_SHADER_GEOMETRY]->xfb_info;
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else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
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xfb_info = pipeline->shaders[MESA_SHADER_TESS_EVAL]->xfb_info;
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else
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xfb_info = pipeline->shaders[MESA_SHADER_VERTEX]->xfb_info;
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pipeline->xfb_used = xfb_info ? xfb_info->buffers_written : 0;
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_STREAMOUT), so) {
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so.RenderingDisable = rs_info->rasterizerDiscardEnable;
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#if GEN_GEN >= 8
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if (xfb_info) {
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so.SOFunctionEnable = true;
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const VkPipelineRasterizationStateStreamCreateInfoEXT *stream_info =
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vk_find_struct_const(rs_info, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT);
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so.RenderStreamSelect = stream_info ?
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stream_info->rasterizationStream : 0;
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so.Buffer0SurfacePitch = xfb_info->strides[0];
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so.Buffer1SurfacePitch = xfb_info->strides[1];
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so.Buffer2SurfacePitch = xfb_info->strides[2];
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so.Buffer3SurfacePitch = xfb_info->strides[3];
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int urb_entry_read_offset = 0;
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int urb_entry_read_length =
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(prog_data->vue_map.num_slots + 1) / 2 - urb_entry_read_offset;
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/* We always read the whole vertex. This could be reduced at some
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* point by reading less and offsetting the register index in the
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* SO_DECLs.
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*/
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so.Stream0VertexReadOffset = urb_entry_read_offset;
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so.Stream0VertexReadLength = urb_entry_read_length - 1;
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so.Stream1VertexReadOffset = urb_entry_read_offset;
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so.Stream1VertexReadLength = urb_entry_read_length - 1;
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so.Stream2VertexReadOffset = urb_entry_read_offset;
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so.Stream2VertexReadLength = urb_entry_read_length - 1;
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so.Stream3VertexReadOffset = urb_entry_read_offset;
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so.Stream3VertexReadLength = urb_entry_read_length - 1;
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}
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#endif /* GEN_GEN >= 8 */
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}
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#if GEN_GEN >= 8
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if (xfb_info) {
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struct GENX(SO_DECL) so_decl[MAX_XFB_STREAMS][128];
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int next_offset[MAX_XFB_BUFFERS] = {0, 0, 0, 0};
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int decls[MAX_XFB_STREAMS] = {0, 0, 0, 0};
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memset(so_decl, 0, sizeof(so_decl));
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for (unsigned i = 0; i < xfb_info->output_count; i++) {
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const nir_xfb_output_info *output = &xfb_info->outputs[i];
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||||
unsigned buffer = output->buffer;
|
||||
unsigned stream = xfb_info->buffer_to_stream[buffer];
|
||||
|
||||
/* Our hardware is unusual in that it requires us to program SO_DECLs
|
||||
* for fake "hole" components, rather than simply taking the offset
|
||||
* for each real varying. Each hole can have size 1, 2, 3, or 4; we
|
||||
* program as many size = 4 holes as we can, then a final hole to
|
||||
* accommodate the final 1, 2, or 3 remaining.
|
||||
*/
|
||||
int hole_dwords = (output->offset - next_offset[buffer]) / 4;
|
||||
while (hole_dwords > 0) {
|
||||
so_decl[stream][decls[stream]++] = (struct GENX(SO_DECL)) {
|
||||
.HoleFlag = 1,
|
||||
.OutputBufferSlot = buffer,
|
||||
.ComponentMask = (1 << MIN2(hole_dwords, 4)) - 1,
|
||||
};
|
||||
hole_dwords -= 4;
|
||||
}
|
||||
|
||||
next_offset[buffer] = output->offset +
|
||||
__builtin_popcount(output->component_mask) * 4;
|
||||
|
||||
so_decl[stream][decls[stream]++] = (struct GENX(SO_DECL)) {
|
||||
.OutputBufferSlot = buffer,
|
||||
.RegisterIndex = vue_map->varying_to_slot[output->location],
|
||||
.ComponentMask = output->component_mask,
|
||||
};
|
||||
}
|
||||
|
||||
int max_decls = 0;
|
||||
for (unsigned s = 0; s < MAX_XFB_STREAMS; s++)
|
||||
max_decls = MAX2(max_decls, decls[s]);
|
||||
|
||||
uint8_t sbs[MAX_XFB_STREAMS] = { };
|
||||
for (unsigned b = 0; b < MAX_XFB_BUFFERS; b++) {
|
||||
if (xfb_info->buffers_written & (1 << b))
|
||||
sbs[xfb_info->buffer_to_stream[b]] |= 1 << b;
|
||||
}
|
||||
|
||||
uint32_t *dw = anv_batch_emitn(&pipeline->batch, 3 + 2 * max_decls,
|
||||
GENX(3DSTATE_SO_DECL_LIST),
|
||||
.StreamtoBufferSelects0 = sbs[0],
|
||||
.StreamtoBufferSelects1 = sbs[1],
|
||||
.StreamtoBufferSelects2 = sbs[2],
|
||||
.StreamtoBufferSelects3 = sbs[3],
|
||||
.NumEntries0 = decls[0],
|
||||
.NumEntries1 = decls[1],
|
||||
.NumEntries2 = decls[2],
|
||||
.NumEntries3 = decls[3]);
|
||||
|
||||
for (int i = 0; i < max_decls; i++) {
|
||||
GENX(SO_DECL_ENTRY_pack)(NULL, dw + 3 + i * 2,
|
||||
&(struct GENX(SO_DECL_ENTRY)) {
|
||||
.Stream0Decl = so_decl[0][i],
|
||||
.Stream1Decl = so_decl[1][i],
|
||||
.Stream2Decl = so_decl[2][i],
|
||||
.Stream3Decl = so_decl[3][i],
|
||||
});
|
||||
}
|
||||
}
|
||||
#endif /* GEN_GEN >= 8 */
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
|
|
Loading…
Reference in New Issue