radeonsi: Fixups for drawing with an index buffer.
Mostly using the DRAW_INDEX_2 type 3 packet instead of DRAW_INDEX, which is no longer supported on SI.
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599140119e
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36abadd0db
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@ -467,7 +467,7 @@ static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
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ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
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}
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void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
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void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
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{
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struct radeon_winsys_cs *cs = ctx->cs;
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unsigned ndwords = 7;
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@ -475,7 +475,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
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uint64_t va;
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if (draw->indices) {
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ndwords = 11;
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ndwords = 12;
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}
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if (ctx->num_cs_dw_queries_suspend)
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ndwords += 6;
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@ -506,13 +506,15 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
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if (draw->indices) {
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va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices);
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va += draw->indices_bo_offset;
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pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
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pm4[5] = va;
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pm4[6] = (va >> 32UL) & 0xFF;
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pm4[7] = draw->vgt_num_indices;
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pm4[8] = draw->vgt_draw_initiator;
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pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
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pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
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pm4[4] = PKT3(PKT3_DRAW_INDEX_2, 4, ctx->predicate_drawing);
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pm4[5] = (draw->indices->b.b.width0 - draw->indices_bo_offset) /
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ctx->index_buffer.index_size;
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pm4[6] = va;
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pm4[7] = (va >> 32UL) & 0xFF;
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pm4[8] = draw->vgt_num_indices;
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pm4[9] = draw->vgt_draw_initiator;
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pm4[10] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
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pm4[11] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
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} else {
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pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
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pm4[5] = draw->vgt_num_indices;
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@ -181,7 +181,6 @@ void r600_get_backend_mask(struct r600_context *ctx);
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void r600_context_fini(struct r600_context *ctx);
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void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
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void r600_context_flush(struct r600_context *ctx, unsigned flags);
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void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
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struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
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void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
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@ -209,7 +208,7 @@ void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *
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void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
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int si_context_init(struct r600_context *ctx);
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void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
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void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
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void _r600_pipe_state_add_reg(struct r600_context *ctx,
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struct r600_pipe_state *state,
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@ -848,9 +848,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
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RADEON_USAGE_READ);
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}
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if (rctx->chip_class >= CAYMAN) {
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evergreen_context_draw(rctx, &rdraw);
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}
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si_context_draw(rctx, &rdraw);
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rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
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