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radeonsi: Fixups for drawing with an index buffer. 

Mostly using the DRAW_INDEX_2 type 3 packet instead of DRAW_INDEX, which is
no longer supported on SI.
This commit is contained in:
Michel Dänzer 2012-05-11 15:26:15 +02:00 committed by Michel Dänzer
parent 599140119e
commit 36abadd0db
3 changed files with 13 additions and 14 deletions
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20
src/gallium/drivers/radeonsi/evergreen_hw_context.c
View File

@ -467,7 +467,7 @@ static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
}
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
{
struct radeon_winsys_cs *cs = ctx->cs;
unsigned ndwords = 7;
@ -475,7 +475,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
uint64_t va;
if (draw->indices) {
ndwords = 11;
ndwords = 12;
}
if (ctx->num_cs_dw_queries_suspend)
ndwords += 6;
@ -506,13 +506,15 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
if (draw->indices) {
va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices);
va += draw->indices_bo_offset;
pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
pm4[5] = va;
pm4[6] = (va >> 32UL) & 0xFF;
pm4[7] = draw->vgt_num_indices;
pm4[8] = draw->vgt_draw_initiator;
pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
pm4[4] = PKT3(PKT3_DRAW_INDEX_2, 4, ctx->predicate_drawing);
pm4[5] = (draw->indices->b.b.width0 - draw->indices_bo_offset) /
ctx->index_buffer.index_size;
pm4[6] = va;
pm4[7] = (va >> 32UL) & 0xFF;
pm4[8] = draw->vgt_num_indices;
pm4[9] = draw->vgt_draw_initiator;
pm4[10] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
pm4[11] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
} else {
pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
pm4[5] = draw->vgt_num_indices;

3
src/gallium/drivers/radeonsi/r600.h
View File

@ -181,7 +181,6 @@ void r600_get_backend_mask(struct r600_context *ctx);
void r600_context_fini(struct r600_context *ctx);
void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
void r600_context_flush(struct r600_context *ctx, unsigned flags);
void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
@ -209,7 +208,7 @@ void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *
void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
int si_context_init(struct r600_context *ctx);
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,

4
src/gallium/drivers/radeonsi/r600_state_common.c
View File

@ -848,9 +848,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
RADEON_USAGE_READ);
}
if (rctx->chip_class >= CAYMAN) {
evergreen_context_draw(rctx, &rdraw);
}
si_context_draw(rctx, &rdraw);
rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;