pan/mdg: Pass the memory type to mir_set_offset directly
We want to add support for more memory types, so replace the is_shared bool with an integer that is directly stored to load_store.arg_1. The new memory type values are off by 0x40, as that bit now comes from the index type. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
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@ -533,7 +533,11 @@ void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block
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void mir_flip(midgard_instruction *ins);
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void mir_compute_temp_count(compiler_context *ctx);
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void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
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#define LDST_GLOBAL 0x3E
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#define LDST_SHARED 0x2E
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#define LDST_SCRATCH 0x2A
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void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, unsigned seg);
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/* 'Intrinsic' move for aliasing */
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@ -220,7 +220,7 @@ mir_match_offset(nir_ssa_def *offset, bool first_free)
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}
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void
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mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared)
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mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, unsigned seg)
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{
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for(unsigned i = 0; i < 16; ++i) {
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ins->swizzle[1][i] = 0;
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@ -232,7 +232,7 @@ mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset,
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bool force_sext = (nir_src_bit_size(*offset) < 64);
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if (!offset->is_ssa) {
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ins->load_store.arg_1 |= is_shared ? 0x6E : 0x7E;
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ins->load_store.arg_1 |= seg;
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ins->src[2] = nir_src_index(ctx, offset);
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ins->src_types[2] = nir_type_uint | nir_src_bit_size(*offset);
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@ -244,14 +244,16 @@ mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset,
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return;
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}
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struct mir_address match = mir_match_offset(offset->ssa, !is_shared);
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bool first_free = (seg == LDST_GLOBAL);
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struct mir_address match = mir_match_offset(offset->ssa, first_free);
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if (match.A.def) {
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ins->src[1] = nir_ssa_index(match.A.def);
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ins->swizzle[1][0] = match.A.comp;
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ins->src_types[1] = nir_type_uint | match.A.def->bit_size;
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} else
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ins->load_store.arg_1 |= is_shared ? 0x6E : 0x7E;
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ins->load_store.arg_1 |= seg;
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if (match.B.def) {
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ins->src[2] = nir_ssa_index(match.B.def);
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@ -1106,7 +1106,7 @@ emit_global(
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bool is_read,
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unsigned srcdest,
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nir_src *offset,
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bool is_shared)
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unsigned seg)
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{
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/* TODO: types */
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@ -1117,7 +1117,7 @@ emit_global(
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else
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ins = m_st_int4(srcdest, 0);
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mir_set_offset(ctx, &ins, offset, is_shared);
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mir_set_offset(ctx, &ins, offset, seg);
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mir_set_intr_mask(instr, &ins, is_read);
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/* Set a valid swizzle for masked out components */
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@ -1178,7 +1178,7 @@ emit_atomic(
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if (is_shared)
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ins.load_store.arg_1 |= 0x6E;
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} else {
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mir_set_offset(ctx, &ins, src_offset, is_shared);
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mir_set_offset(ctx, &ins, src_offset, is_shared ? LDST_SHARED : LDST_GLOBAL);
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}
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mir_set_intr_mask(&instr->instr, &ins, true);
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@ -1555,7 +1555,8 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
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uint32_t uindex = nir_src_as_uint(index) + 1;
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emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
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} else if (is_global || is_shared) {
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emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
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unsigned seg = is_global ? LDST_GLOBAL : (is_shared ? LDST_SHARED : LDST_SCRATCH);
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emit_global(ctx, &instr->instr, true, reg, src_offset, seg);
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} else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
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emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
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} else if (ctx->is_blend) {
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@ -1782,7 +1783,13 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
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reg = nir_src_index(ctx, &instr->src[0]);
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emit_explicit_constant(ctx, reg, reg);
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emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
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unsigned seg;
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if (instr->intrinsic == nir_intrinsic_store_global)
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seg = LDST_GLOBAL;
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else if (instr->intrinsic == nir_intrinsic_store_shared)
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seg = LDST_SHARED;
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emit_global(ctx, &instr->instr, false, reg, &instr->src[1], seg);
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break;
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case nir_intrinsic_load_ssbo_address:
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