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radeonsi: rename r600_resource_texture to r600_texture 

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2013-08-05 03:42:11 +02:00
parent 128819d394
commit 363b2805f7
7 changed files with 48 additions and 48 deletions
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22
src/gallium/drivers/radeonsi/r600_blit.c
View File

@ -101,8 +101,8 @@ static void r600_blitter_end(struct pipe_context *ctx)
}
void si_blit_uncompress_depth(struct pipe_context *ctx,
struct r600_resource_texture *texture,
struct r600_resource_texture *staging,
struct r600_texture *texture,
struct r600_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer)
{
@ -111,7 +111,7 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
float depth = 1.0f;
const struct util_format_description *desc;
void *custom_dsa;
struct r600_resource_texture *flushed_depth_texture = staging ?
struct r600_texture *flushed_depth_texture = staging ?
staging : texture->flushed_depth_texture;
if (!staging && !texture->dirty_db_mask)
@ -172,7 +172,7 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
}
static void si_blit_decompress_depth_in_place(struct r600_context *rctx,
struct r600_resource_texture *texture,
struct r600_texture *texture,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer)
{
@ -222,12 +222,12 @@ void si_flush_depth_textures(struct r600_context *rctx,
for (i = 0; i < textures->n_views; ++i) {
struct pipe_sampler_view *view;
struct r600_resource_texture *tex;
struct r600_texture *tex;
view = &textures->views[i]->base;
if (!view) continue;
tex = (struct r600_resource_texture *)view->texture;
tex = (struct r600_texture *)view->texture;
if (!tex->is_depth || tex->is_flushing_texture)
continue;
@ -294,7 +294,7 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
unsigned level,
struct texture_orig_info *orig)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
struct r600_texture *rtex = (struct r600_texture*)tex;
unsigned pixsize = util_format_get_blocksize(rtex->real_format);
int new_format;
int new_height, new_width;
@ -329,7 +329,7 @@ static void r600_change_format(struct pipe_resource *tex,
struct texture_orig_info *orig,
enum pipe_format format)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
struct r600_texture *rtex = (struct r600_texture*)tex;
orig->format = tex->format;
orig->width0 = tex->width0;
@ -346,7 +346,7 @@ static void r600_reset_blittable_to_orig(struct pipe_resource *tex,
unsigned level,
struct texture_orig_info *orig)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
struct r600_texture *rtex = (struct r600_texture*)tex;
tex->format = orig->format;
tex->width0 = orig->width0;
@ -366,7 +366,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
const struct pipe_box *src_box)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_resource_texture *rsrc = (struct r600_resource_texture*)src;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct texture_orig_info orig_info[2];
struct pipe_box sbox;
const struct pipe_box *psbox = src_box;
@ -467,7 +467,7 @@ static void si_blit(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct r600_context *rctx = (struct r600_context*)ctx;
struct r600_resource_texture *rsrc = (struct r600_resource_texture*)info->src.resource;
struct r600_texture *rsrc = (struct r600_texture*)info->src.resource;
assert(util_blitter_is_blit_supported(rctx->blitter, info));

6
src/gallium/drivers/radeonsi/r600_resource.h
View File

@ -39,7 +39,7 @@ struct r600_transfer {
struct pipe_resource *staging;
};
struct r600_resource_texture {
struct r600_texture {
struct si_resource resource;
/* If this resource is a depth-stencil buffer on evergreen, this contains
@ -50,7 +50,7 @@ struct r600_resource_texture {
unsigned pitch_override;
unsigned is_depth;
unsigned dirty_db_mask; /* each bit says if that miplevel is dirty */
struct r600_resource_texture *flushed_depth_texture;
struct r600_texture *flushed_depth_texture;
boolean is_flushing_texture;
struct radeon_surface surface;
};
@ -70,7 +70,7 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_resource_texture **staging);
struct r600_texture **staging);
struct r600_context;

34
src/gallium/drivers/radeonsi/r600_texture.c
View File

@ -62,7 +62,7 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
0, &sbox);
}
static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
static unsigned r600_texture_get_offset(struct r600_texture *rtex,
unsigned level, unsigned layer)
{
return rtex->surface.level[level].offset +
@ -161,7 +161,7 @@ static int r600_init_surface(struct r600_screen *rscreen,
}
static int r600_setup_surface(struct pipe_screen *screen,
struct r600_resource_texture *rtex,
struct r600_texture *rtex,
unsigned array_mode,
unsigned pitch_in_bytes_override)
{
@ -191,7 +191,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
struct pipe_resource *ptex,
struct winsys_handle *whandle)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct si_resource *resource = &rtex->resource;
struct radeon_surface *surface = &rtex->surface;
struct r600_screen *rscreen = (struct r600_screen*)screen;
@ -215,7 +215,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
static void r600_texture_destroy(struct pipe_screen *screen,
struct pipe_resource *ptex)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct si_resource *resource = &rtex->resource;
if (rtex->flushed_depth_texture)
@ -233,7 +233,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer **ptransfer)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_transfer *trans;
boolean use_staging_texture = FALSE;
struct radeon_winsys_cs_handle *buf;
@ -281,7 +281,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
*/
/* XXX: when discard is true, no need to read back from depth texture
*/
struct r600_resource_texture *staging_depth;
struct r600_texture *staging_depth;
if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
R600_ERR("failed to create temporary texture to hold untiled copy\n");
@ -299,7 +299,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
trans->staging = &staging_depth->resource.b.b;
} else if (use_staging_texture) {
struct pipe_resource resource;
struct r600_resource_texture *staging;
struct r600_texture *staging;
memset(&resource, 0, sizeof(resource));
resource.format = texture->format;
@ -328,7 +328,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
default:;
}
/* Create the temporary texture. */
staging = (struct r600_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource);
staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
if (staging == NULL) {
R600_ERR("failed to create temporary texture to hold untiled copy\n");
pipe_resource_reference(&trans->transfer.resource, NULL);
@ -379,7 +379,7 @@ static void si_texture_transfer_unmap(struct pipe_context *ctx,
struct r600_context *rctx = (struct r600_context*)ctx;
struct radeon_winsys_cs_handle *buf;
struct pipe_resource *texture = transfer->resource;
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct r600_texture *rtex = (struct r600_texture*)texture;
if (rtransfer->staging) {
buf = si_resource(rtransfer->staging)->cs_buf;
@ -418,7 +418,7 @@ static const struct u_resource_vtbl r600_texture_vtbl =
DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE);
static struct r600_resource_texture *
static struct r600_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned array_mode,
@ -428,12 +428,12 @@ r600_texture_create_object(struct pipe_screen *screen,
boolean alloc_bo,
struct radeon_surface *surface)
{
struct r600_resource_texture *rtex;
struct r600_texture *rtex;
struct si_resource *resource;
struct r600_screen *rscreen = (struct r600_screen*)screen;
int r;
rtex = CALLOC_STRUCT(r600_resource_texture);
rtex = CALLOC_STRUCT(r600_texture);
if (rtex == NULL)
return NULL;
@ -556,7 +556,7 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface *surf_tmpl)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
unsigned level = surf_tmpl->u.tex.level;
@ -634,11 +634,11 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_resource_texture **staging)
struct r600_texture **staging)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct r600_texture *rtex = (struct r600_texture*)texture;
struct pipe_resource resource;
struct r600_resource_texture **flushed_depth_texture = staging ?
struct r600_texture **flushed_depth_texture = staging ?
staging : &rtex->flushed_depth_texture;
if (!staging && rtex->flushed_depth_texture)
@ -661,7 +661,7 @@ bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
else
rtex->dirty_db_mask = (1 << (resource.last_level+1)) - 1;
*flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
*flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
if (*flushed_depth_texture == NULL) {
R600_ERR("failed to create temporary texture to hold flushed depth\n");
return false;

4
src/gallium/drivers/radeonsi/radeonsi_pipe.h
View File

@ -212,8 +212,8 @@ struct r600_context {
/* r600_blit.c */
void si_init_blit_functions(struct r600_context *rctx);
void si_blit_uncompress_depth(struct pipe_context *ctx,
struct r600_resource_texture *texture,
struct r600_resource_texture *staging,
struct r600_texture *texture,
struct r600_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer);
void si_flush_depth_textures(struct r600_context *rctx,

12
src/gallium/drivers/radeonsi/radeonsi_uvd.c
View File

@ -55,7 +55,7 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe
const struct pipe_video_buffer *tmpl)
{
struct r600_context *ctx = (struct r600_context *)pipe;
struct r600_resource_texture *resources[VL_NUM_COMPONENTS] = {};
struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
struct radeon_surface *surfaces[VL_NUM_COMPONENTS] = {};
struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
const enum pipe_format *resource_formats;
@ -78,7 +78,7 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe
vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_STATIC, 0);
/* TODO: Setting the transfer flag is only a workaround till we get tiling working */
templ.flags = R600_RESOURCE_FLAG_TRANSFER;
resources[0] = (struct r600_resource_texture *)
resources[0] = (struct r600_texture *)
pipe->screen->resource_create(pipe->screen, &templ);
if (!resources[0])
goto error;
@ -86,7 +86,7 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe
if (resource_formats[1] != PIPE_FORMAT_NONE) {
vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_STATIC, 1);
templ.flags = R600_RESOURCE_FLAG_TRANSFER;
resources[1] = (struct r600_resource_texture *)
resources[1] = (struct r600_texture *)
pipe->screen->resource_create(pipe->screen, &templ);
if (!resources[1])
goto error;
@ -95,7 +95,7 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe
if (resource_formats[2] != PIPE_FORMAT_NONE) {
vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_STATIC, 2);
templ.flags = R600_RESOURCE_FLAG_TRANSFER;
resources[2] = (struct r600_resource_texture *)
resources[2] = (struct r600_texture *)
pipe->screen->resource_create(pipe->screen, &templ);
if (!resources[2])
goto error;
@ -133,8 +133,8 @@ error:
/* set the decoding target buffer offsets */
static struct radeon_winsys_cs_handle* radeonsi_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
{
struct r600_resource_texture *luma = (struct r600_resource_texture *)buf->resources[0];
struct r600_resource_texture *chroma = (struct r600_resource_texture *)buf->resources[1];
struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
msg->body.decode.dt_field_mode = buf->base.interlaced;

16
src/gallium/drivers/radeonsi/si_state.c
View File

@ -1709,7 +1709,7 @@ boolean si_is_format_supported(struct pipe_screen *screen,
return retval == usage;
}
static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil)
static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
{
unsigned tile_mode_index = 0;
@ -1728,7 +1728,7 @@ static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned
static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
const struct pipe_framebuffer_state *state, int cb)
{
struct r600_resource_texture *rtex;
struct r600_texture *rtex;
struct r600_surface *surf;
unsigned level = state->cbufs[cb]->u.tex.level;
unsigned pitch, slice;
@ -1742,7 +1742,7 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
unsigned max_comp_size;
surf = (struct r600_surface *)state->cbufs[cb];
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
rtex = (struct r600_texture*)state->cbufs[cb]->texture;
offset = rtex->surface.level[level].offset;
if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
@ -1865,7 +1865,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
const struct pipe_framebuffer_state *state)
{
struct r600_screen *rscreen = rctx->screen;
struct r600_resource_texture *rtex;
struct r600_texture *rtex;
struct r600_surface *surf;
unsigned level, pitch, slice, format, tile_mode_index, array_mode;
unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
@ -1880,7 +1880,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
surf = (struct r600_surface *)state->zsbuf;
level = surf->base.u.tex.level;
rtex = (struct r600_resource_texture*)surf->base.texture;
rtex = (struct r600_texture*)surf->base.texture;
format = si_translate_dbformat(rtex->real_format);
@ -2243,7 +2243,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
const struct pipe_sampler_view *state)
{
struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
struct r600_texture *tmp = (struct r600_texture*)texture;
const struct util_format_description *desc;
unsigned format, num_format;
uint32_t pitch = 0;
@ -2510,8 +2510,8 @@ static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
views[i]);
if (views[i]) {
struct r600_resource_texture *rtex =
(struct r600_resource_texture*)views[i]->texture;
struct r600_texture *rtex =
(struct r600_texture*)views[i]->texture;
if (rtex->is_depth && !rtex->is_flushing_texture) {
samplers->depth_texture_mask |= 1 << i;

2
src/gallium/drivers/radeonsi/si_state_draw.c
View File

@ -724,7 +724,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* Set the depth buffer as dirty. */
if (rctx->framebuffer.zsbuf) {
struct pipe_surface *surf = rctx->framebuffer.zsbuf;
struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_db_mask |= 1 << surf->u.tex.level;
}