From 361b3fee3c5ee38821d96660d68ebec2e31e5f47 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 22 Sep 2021 15:06:58 +0300 Subject: [PATCH] intel: move away from booleans to identify platforms v2: Drop changes around GFX_VERx10 == 75 (Luis) v3: Replace (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT) by (devinfo->platform == INTEL_PLATFORM_IVB) Replace (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X) by (devinfo->verx10 >= 45) Replace (devinfo->platform != INTEL_PLATFORM_G4X) by (devinfo->verx10 != 45) v4: Fix crocus typo v5: Rebase v6: Add GFX3, ILK & I965 platforms (Jordan) Move ifdef to code expressions (Jordan) Signed-off-by: Lionel Landwerlin Reviewed-by: Jordan Justen Part-of: --- src/gallium/drivers/crocus/crocus_batch.c | 2 +- .../drivers/crocus/crocus_pipe_control.c | 2 +- src/gallium/drivers/crocus/crocus_screen.c | 2 +- src/gallium/drivers/crocus/crocus_state.c | 18 +-- src/gallium/drivers/iris/iris_screen.c | 2 +- src/gallium/drivers/iris/iris_state.c | 4 +- src/intel/common/intel_l3_config.c | 11 +- src/intel/common/tests/mi_builder_test.cpp | 3 +- src/intel/compiler/brw_clip_util.c | 2 +- src/intel/compiler/brw_disasm.c | 4 +- src/intel/compiler/brw_eu.h | 14 +-- src/intel/compiler/brw_eu_compact.c | 21 ++-- src/intel/compiler/brw_eu_emit.c | 2 +- src/intel/compiler/brw_eu_validate.c | 16 +-- src/intel/compiler/brw_fs.cpp | 12 +- src/intel/compiler/brw_fs_generator.cpp | 15 +-- src/intel/compiler/brw_fs_lower_regioning.cpp | 3 +- src/intel/compiler/brw_fs_nir.cpp | 4 +- src/intel/compiler/brw_inst.h | 9 +- src/intel/compiler/brw_ir_fs.h | 3 +- src/intel/compiler/brw_ir_performance.cpp | 48 ++++---- src/intel/compiler/brw_nir.c | 2 +- .../compiler/brw_nir_lower_storage_image.c | 2 +- .../compiler/brw_schedule_instructions.cpp | 2 +- src/intel/compiler/brw_vec4_generator.cpp | 14 ++- src/intel/compiler/brw_vec4_nir.cpp | 2 +- .../compiler/brw_vec4_surface_builder.cpp | 4 +- src/intel/compiler/brw_vec4_visitor.cpp | 2 +- src/intel/compiler/test_eu_compact.cpp | 4 +- src/intel/compiler/test_eu_validate.cpp | 25 ++-- src/intel/dev/intel_device_info.c | 111 +++++++++--------- src/intel/dev/intel_device_info.h | 49 +++++--- src/intel/dev/intel_device_info_test.c | 2 + src/intel/isl/isl.c | 14 +-- src/intel/isl/isl.h | 8 +- src/intel/isl/isl_format.c | 8 +- src/intel/isl/isl_gfx7.c | 2 +- src/intel/isl/isl_surface_state.c | 2 +- src/intel/perf/intel_perf.c | 51 ++++---- src/intel/perf/intel_perf_mdapi.c | 4 +- src/intel/tools/intel_dump_gpu.c | 6 +- src/intel/tools/intel_noop_drm_shim.c | 4 +- src/intel/vulkan/anv_device.c | 15 +-- src/intel/vulkan/genX_cmd_buffer.c | 2 +- src/intel/vulkan/genX_pipeline.c | 2 +- src/intel/vulkan/genX_query.c | 4 +- src/intel/vulkan/genX_state.c | 6 +- src/intel/vulkan/gfx8_cmd_buffer.c | 2 +- src/mesa/drivers/dri/i965/brw_batch.c | 2 +- src/mesa/drivers/dri/i965/brw_blorp.c | 4 +- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/brw_curbe.c | 2 +- src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +- src/mesa/drivers/dri/i965/brw_extensions.c | 9 +- src/mesa/drivers/dri/i965/brw_mipmap_tree.c | 2 +- src/mesa/drivers/dri/i965/brw_mipmap_tree.h | 2 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 10 +- src/mesa/drivers/dri/i965/brw_pipe_control.c | 10 +- src/mesa/drivers/dri/i965/brw_screen.c | 12 +- src/mesa/drivers/dri/i965/brw_state_upload.c | 4 +- src/mesa/drivers/dri/i965/brw_urb.c | 2 +- src/mesa/drivers/dri/i965/brw_wm.c | 5 +- .../drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/genX_state_upload.c | 10 +- src/mesa/drivers/dri/i965/gfx6_queryobj.c | 2 +- src/mesa/drivers/dri/i965/gfx7_l3_state.c | 8 +- src/mesa/drivers/dri/i965/gfx7_urb.c | 10 +- src/mesa/drivers/dri/i965/hsw_queryobj.c | 2 +- src/mesa/drivers/dri/i965/hsw_sol.c | 4 +- 69 files changed, 346 insertions(+), 306 deletions(-) diff --git a/src/gallium/drivers/crocus/crocus_batch.c b/src/gallium/drivers/crocus/crocus_batch.c index d029bd0e323..6f0026d05e5 100644 --- a/src/gallium/drivers/crocus/crocus_batch.c +++ b/src/gallium/drivers/crocus/crocus_batch.c @@ -67,7 +67,7 @@ * or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may * need an extra 4 bytes to pad out to the nearest QWord. So reserve 16. */ -#define BATCH_RESERVED(devinfo) ((devinfo)->is_haswell ? 32 : 16) +#define BATCH_RESERVED(devinfo) ((devinfo)->platform == INTEL_PLATFORM_HSW ? 32 : 16) static void crocus_batch_reset(struct crocus_batch *batch); diff --git a/src/gallium/drivers/crocus/crocus_pipe_control.c b/src/gallium/drivers/crocus/crocus_pipe_control.c index bd2e459aab6..7a1101bf04b 100644 --- a/src/gallium/drivers/crocus/crocus_pipe_control.c +++ b/src/gallium/drivers/crocus/crocus_pipe_control.c @@ -189,7 +189,7 @@ crocus_emit_end_of_pipe_sync(struct crocus_batch *batch, batch->ice->workaround_bo, batch->ice->workaround_offset, 0); - if (batch->screen->devinfo.is_haswell) { + if (batch->screen->devinfo.platform == INTEL_PLATFORM_HSW) { #define GEN7_3DPRIM_START_INSTANCE 0x243C batch->screen->vtbl.load_register_mem32(batch, GEN7_3DPRIM_START_INSTANCE, batch->ice->workaround_bo, diff --git a/src/gallium/drivers/crocus/crocus_screen.c b/src/gallium/drivers/crocus/crocus_screen.c index 43bb4ed7047..a92db345333 100644 --- a/src/gallium/drivers/crocus/crocus_screen.c +++ b/src/gallium/drivers/crocus/crocus_screen.c @@ -734,7 +734,7 @@ crocus_screen_create(int fd, const struct pipe_screen_config *config) if (screen->devinfo.ver == 8) { /* bind to cherryview or bdw if forced */ - if (!screen->devinfo.is_cherryview && + if (screen->devinfo.platform != INTEL_PLATFORM_CHV && !getenv("CROCUS_GEN8")) return NULL; } diff --git a/src/gallium/drivers/crocus/crocus_state.c b/src/gallium/drivers/crocus/crocus_state.c index 59e88e6f230..c54fb7e48b8 100644 --- a/src/gallium/drivers/crocus/crocus_state.c +++ b/src/gallium/drivers/crocus/crocus_state.c @@ -1125,11 +1125,11 @@ setup_l3_config(struct crocus_batch *batch, const struct intel_l3_config *cfg) * client (URB for all validated configurations) set to the * lower-bandwidth 2-bank address hashing mode. */ - const bool urb_low_bw = has_slm && !devinfo->is_baytrail; + const bool urb_low_bw = has_slm && devinfo->platform != INTEL_PLATFORM_BYT; assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]); /* Minimum number of ways that can be allocated to the URB. */ - const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0); + const unsigned n0_urb = (devinfo->platform == INTEL_PLATFORM_BYT ? 32 : 0); assert(cfg->n[INTEL_L3P_URB] >= n0_urb); uint32_t l3sqcr1, l3cr2, l3cr3; @@ -1143,7 +1143,7 @@ setup_l3_config(struct crocus_batch *batch, const struct intel_l3_config *cfg) reg.L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT; #else reg.L3SQGeneralPriorityCreditInitialization = - devinfo->is_baytrail ? BYT_SQGPCI_DEFAULT : SQGPCI_DEFAULT; + devinfo->platform == INTEL_PLATFORM_BYT ? BYT_SQGPCI_DEFAULT : SQGPCI_DEFAULT; #endif reg.L3SQHighPriorityCreditInitialization = SQHPCI_DEFAULT; }; @@ -1348,7 +1348,7 @@ crocus_alloc_push_constants(struct crocus_batch *batch) * * No such restriction exists for Haswell or Baytrail. */ - if (!(GFX_VERx10 == 75) && !batch->screen->devinfo.is_baytrail) + if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB) gen7_emit_cs_stall_flush(batch); } #endif @@ -2025,7 +2025,7 @@ crocus_create_rasterizer_state(struct pipe_context *ctx, #endif #if GFX_VER == 8 struct crocus_screen *screen = (struct crocus_screen *)ctx->screen; - if (screen->devinfo.is_cherryview) + if (screen->devinfo.platform == INTEL_PLATFORM_CHV) sf.CHVLineWidth = line_width; else sf.LineWidth = line_width; @@ -3663,7 +3663,7 @@ crocus_set_vertex_buffers(struct pipe_context *ctx, struct crocus_context *ice = (struct crocus_context *) ctx; struct crocus_screen *screen = (struct crocus_screen *) ctx->screen; const unsigned padding = - (GFX_VERx10 < 75 && !screen->devinfo.is_baytrail) * 2; + (GFX_VERx10 < 75 && screen->devinfo.platform != INTEL_PLATFORM_BYT) * 2; ice->state.bound_vertex_buffers &= ~u_bit_consecutive64(start_slot, count + unbind_num_trailing_slots); @@ -5704,7 +5704,7 @@ emit_push_constant_packets(struct crocus_context *ice, #if GFX_VER == 7 if (stage == MESA_SHADER_VERTEX) { - if (!(GFX_VERx10 == 75) && !batch->screen->devinfo.is_baytrail) + if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB) gen7_emit_vs_workaround_flush(batch); } #endif @@ -6088,7 +6088,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice, entries, start, NULL, &constrained); #if GFX_VER == 7 - if (GFX_VERx10 < 75 && !devinfo->is_baytrail) + if (devinfo->platform == INTEL_PLATFORM_IVB) gen7_emit_vs_workaround_flush(batch); #endif for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { @@ -6731,7 +6731,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice, const struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(shader->prog_data); const struct brw_stage_prog_data *prog_data = &vue_prog_data->base; #if GFX_VER == 7 - if (batch->screen->devinfo.is_ivybridge) + if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB) gen7_emit_vs_workaround_flush(batch); #endif diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index 01c1a46607e..44113d91410 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -785,7 +785,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config) p_atomic_set(&screen->refcount, 1); - if (screen->devinfo.ver < 8 || screen->devinfo.is_cherryview) + if (screen->devinfo.ver < 8 || screen->devinfo.platform == INTEL_PLATFORM_CHV) return NULL; driParseConfigFiles(config->options, config->options_info, 0, "iris", diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 342bb21d94e..0ea5205c316 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1011,7 +1011,7 @@ iris_init_render_context(struct iris_batch *batch) reg.PartialResolveDisableInVCMask = true; } - if (devinfo->is_geminilake) + if (devinfo->platform == INTEL_PLATFORM_GLK) init_glk_barrier_mode(batch, GLK_BARRIER_MODE_3D_HULL); #endif @@ -1112,7 +1112,7 @@ iris_init_compute_context(struct iris_batch *batch) #endif #if GFX_VER == 9 - if (devinfo->is_geminilake) + if (devinfo->platform == INTEL_PLATFORM_GLK) init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU); #endif diff --git a/src/intel/common/intel_l3_config.c b/src/intel/common/intel_l3_config.c index fabf2bb8278..d752fcf12b6 100644 --- a/src/intel/common/intel_l3_config.c +++ b/src/intel/common/intel_l3_config.c @@ -165,10 +165,10 @@ get_l3_list(const struct intel_device_info *devinfo) { switch (devinfo->ver) { case 7: - return (devinfo->is_baytrail ? &vlv_l3_list : &ivb_l3_list); + return (devinfo->platform == INTEL_PLATFORM_BYT ? &vlv_l3_list : &ivb_l3_list); case 8: - return (devinfo->is_cherryview ? &chv_l3_list : &bdw_l3_list); + return (devinfo->platform == INTEL_PLATFORM_CHV ? &chv_l3_list : &bdw_l3_list); case 9: if (devinfo->l3_banks == 1) @@ -179,7 +179,8 @@ get_l3_list(const struct intel_device_info *devinfo) return &icl_l3_list; case 12: - if (devinfo->is_dg1 || devinfo->is_dg2) + if (devinfo->platform == INTEL_PLATFORM_DG1 || + devinfo->platform == INTEL_PLATFORM_DG2) return &empty_l3_list; else return &tgl_l3_list; @@ -269,7 +270,7 @@ intel_get_default_l3_weights(const struct intel_device_info *devinfo, w.w[INTEL_L3P_ALL] = 1.0; } else { w.w[INTEL_L3P_DC] = needs_dc ? 0.1 : 0; - w.w[INTEL_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0; + w.w[INTEL_L3P_RO] = devinfo->platform == INTEL_PLATFORM_BYT ? 0.5 : 1.0; } return norm_l3_weights(w); @@ -352,7 +353,7 @@ intel_get_l3_config_urb_size(const struct intel_device_info *devinfo, const struct intel_l3_config *cfg) { /* We don't have to program the URB size in DG1, it's a fixed value. */ - if (devinfo->is_dg1) + if (devinfo->platform == INTEL_PLATFORM_DG1) return devinfo->urb.size; /* From the SKL "L3 Allocation and Programming" documentation: diff --git a/src/intel/common/tests/mi_builder_test.cpp b/src/intel/common/tests/mi_builder_test.cpp index 4d830a55cb2..343ecb628ce 100644 --- a/src/intel/common/tests/mi_builder_test.cpp +++ b/src/intel/common/tests/mi_builder_test.cpp @@ -194,7 +194,8 @@ mi_builder_test::SetUp() (void *)&getparam), 0) << strerror(errno); ASSERT_TRUE(intel_get_device_info_from_pci_id(device_id, &devinfo)); - if (devinfo.ver != GFX_VER || devinfo.is_haswell != (GFX_VERx10 == 75)) { + if (devinfo.ver != GFX_VER || + (devinfo.platform == INTEL_PLATFORM_HSW) != (GFX_VERx10 == 75)) { close(fd); fd = -1; continue; diff --git a/src/intel/compiler/brw_clip_util.c b/src/intel/compiler/brw_clip_util.c index 1f334d2bcb9..32c70006933 100644 --- a/src/intel/compiler/brw_clip_util.c +++ b/src/intel/compiler/brw_clip_util.c @@ -424,7 +424,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c ) /* Rearrange userclip outcodes so that they come directly after * the fixed plane bits. */ - if (p->devinfo->ver == 5 || p->devinfo->is_g4x) + if (p->devinfo->ver == 5 || p->devinfo->verx10 == 45) brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14)); else brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14)); diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index acbe9d6f94d..9b1d9017fb6 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -2100,7 +2100,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo, brw_sampler_desc_binding_table_index(devinfo, imm_desc), brw_sampler_desc_sampler(devinfo, imm_desc), brw_sampler_desc_msg_type(devinfo, imm_desc)); - if (!devinfo->is_g4x) { + if (devinfo->verx10 != 45) { err |= control(file, "sampler target format", sampler_target_format, brw_sampler_desc_return_format(devinfo, imm_desc), @@ -2120,7 +2120,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo, devinfo->ver >= 7 ? 0u : brw_dp_write_desc_write_commit(devinfo, imm_desc)); } else { - bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x; + bool is_965 = devinfo->verx10 == 40; err |= control(file, "DP read message type", is_965 ? gfx4_dp_read_port_msg_type : g45_dp_read_port_msg_type, diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 04256257533..11f2734e175 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -402,7 +402,7 @@ brw_sampler_desc(const struct intel_device_info *devinfo, else if (devinfo->ver >= 5) return (desc | SET_BITS(msg_type, 15, 12) | SET_BITS(simd_mode, 17, 16)); - else if (devinfo->is_g4x) + else if (devinfo->verx10 >= 45) return desc | SET_BITS(msg_type, 15, 12); else return (desc | SET_BITS(return_format, 13, 12) | @@ -429,7 +429,7 @@ brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc { if (devinfo->ver >= 7) return GET_BITS(desc, 16, 12); - else if (devinfo->ver >= 5 || devinfo->is_g4x) + else if (devinfo->verx10 >= 45) return GET_BITS(desc, 15, 12); else return GET_BITS(desc, 15, 14); @@ -450,7 +450,7 @@ static inline unsigned brw_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver == 4 && !devinfo->is_g4x); + assert(devinfo->verx10 == 40); return GET_BITS(desc, 13, 12); } @@ -522,7 +522,7 @@ brw_dp_read_desc(const struct intel_device_info *devinfo, { if (devinfo->ver >= 6) return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control); - else if (devinfo->ver >= 5 || devinfo->is_g4x) + else if (devinfo->verx10 >= 45) return (SET_BITS(binding_table_index, 7, 0) | SET_BITS(msg_control, 10, 8) | SET_BITS(msg_type, 13, 11) | @@ -540,7 +540,7 @@ brw_dp_read_desc_msg_type(const struct intel_device_info *devinfo, { if (devinfo->ver >= 6) return brw_dp_desc_msg_type(devinfo, desc); - else if (devinfo->ver >= 5 || devinfo->is_g4x) + else if (devinfo->verx10 >= 45) return GET_BITS(desc, 13, 11); else return GET_BITS(desc, 13, 12); @@ -552,7 +552,7 @@ brw_dp_read_desc_msg_control(const struct intel_device_info *devinfo, { if (devinfo->ver >= 6) return brw_dp_desc_msg_control(devinfo, desc); - else if (devinfo->ver >= 5 || devinfo->is_g4x) + else if (devinfo->verx10 >= 45) return GET_BITS(desc, 10, 8); else return GET_BITS(desc, 11, 8); @@ -779,7 +779,7 @@ brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo, } else { if (devinfo->ver >= 7) { msg_type = GFX7_DATAPORT_DC_DWORD_SCATTERED_READ; - } else if (devinfo->ver > 4 || devinfo->is_g4x) { + } else if (devinfo->verx10 >= 45) { msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; } else { msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index 1bda759b185..38c9279ef9f 100644 --- a/src/intel/compiler/brw_eu_compact.c +++ b/src/intel/compiler/brw_eu_compact.c @@ -1331,7 +1331,7 @@ set_3src_control_index(const struct intel_device_info *devinfo, (brw_inst_bits(src, 34, 32) << 21) | /* 3b */ (brw_inst_bits(src, 28, 8)); /* 21b */ - if (devinfo->ver >= 9 || devinfo->is_cherryview) { + if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { uncompacted |= brw_inst_bits(src, 36, 35) << 24; /* 2b */ } @@ -1392,7 +1392,7 @@ set_3src_source_index(const struct intel_device_info *devinfo, (brw_inst_bits(src, 72, 65) << 19) | /* 8b */ (brw_inst_bits(src, 55, 37)); /* 19b */ - if (devinfo->ver >= 9 || devinfo->is_cherryview) { + if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { uncompacted |= (brw_inst_bits(src, 126, 125) << 47) | /* 2b */ (brw_inst_bits(src, 105, 104) << 45) | /* 2b */ @@ -1480,7 +1480,7 @@ has_3src_unmapped_bits(const struct intel_device_info *devinfo, */ if (devinfo->ver >= 12) { assert(!brw_inst_bits(src, 7, 7)); - } else if (devinfo->ver >= 9 || devinfo->is_cherryview) { + } else if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { assert(!brw_inst_bits(src, 127, 127) && !brw_inst_bits(src, 7, 7)); } else { @@ -1728,7 +1728,7 @@ precompact(const struct intel_device_info *devinfo, brw_inst inst) * immediate we set. */ if (devinfo->ver >= 6 && - !(devinfo->is_haswell && + !(devinfo->platform == INTEL_PLATFORM_HSW && brw_inst_opcode(devinfo, &inst) == BRW_OPCODE_DIM) && !(devinfo->ver >= 8 && (brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF || @@ -2082,7 +2082,7 @@ set_uncompacted_3src_control_index(const struct compaction_state *c, brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7); brw_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff); - if (devinfo->ver >= 9 || devinfo->is_cherryview) + if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) brw_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3); } } @@ -2125,7 +2125,7 @@ set_uncompacted_3src_source_index(const struct intel_device_info *devinfo, brw_inst_set_bits(dst, 72, 65, (uncompacted >> 19) & 0xff); brw_inst_set_bits(dst, 55, 37, (uncompacted >> 0) & 0x7ffff); - if (devinfo->ver >= 9 || devinfo->is_cherryview) { + if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { brw_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3); brw_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3); brw_inst_set_bits(dst, 84, 84, (uncompacted >> 44) & 0x1); @@ -2339,13 +2339,13 @@ static void update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn, int this_old_ip, int *compacted_counts) { - assert(devinfo->ver == 5 || devinfo->is_g4x); + assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X); /* Jump Count is in units of: * - uncompacted instructions on G45; and * - compacted instructions on Gfx5. */ - int shift = devinfo->is_g4x ? 1 : 0; + int shift = devinfo->platform == INTEL_PLATFORM_G4X ? 1 : 0; int jump_count_compacted = brw_inst_gfx4_jump_count(devinfo, insn) << shift; @@ -2462,7 +2462,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, */ int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1]; - if (devinfo->ver == 4 && !devinfo->is_g4x) + if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X) return; struct compaction_state c; @@ -2495,7 +2495,8 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset, offset += sizeof(brw_compact_inst); } else { /* All uncompacted instructions need to be aligned on G45. */ - if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){ + if ((offset & sizeof(brw_compact_inst)) != 0 && + devinfo->platform == INTEL_PLATFORM_G4X) { brw_compact_inst *align = store + offset; memset(align, 0, sizeof(*align)); brw_compact_inst_set_hw_opcode( diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index a8e19cbf0c9..a88be5aba4c 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3544,7 +3544,7 @@ brw_broadcast(struct brw_codegen *p, /* Use indirect addressing to fetch the specified component. */ if (type_sz(src.type) > 4 && - (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) || + (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_float)) { /* From the Cherryview PRM Vol 7. "Register Region Restrictions": * diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 68d41e3e661..8e36e655d09 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -862,7 +862,8 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi ERROR_IF(subreg % 4 != 0, "Conversions between integer and half-float must be " "aligned to a DWord on the destination"); - } else if ((devinfo->is_cherryview || devinfo->ver >= 9) && + } else if ((devinfo->platform == INTEL_PLATFORM_CHV || + devinfo->ver >= 9) && dst_type == BRW_REGISTER_TYPE_HF) { unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); ERROR_IF(dst_stride != 2 && @@ -881,7 +882,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi */ bool validate_dst_size_and_exec_size_ratio = !is_mixed_float(devinfo, inst) || - !(devinfo->is_cherryview || devinfo->ver >= 9); + !(devinfo->platform == INTEL_PLATFORM_CHV || devinfo->ver >= 9); if (validate_dst_size_and_exec_size_ratio && exec_type_size > dst_type_size) { @@ -900,7 +901,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi * Implementation Restriction: The relaxed alignment rule for byte * destination (#10.5) is not supported. */ - if ((devinfo->ver > 4 || devinfo->is_g4x) && dst_type_is_byte) { + if (devinfo->verx10 >= 45 && dst_type_is_byte) { ERROR_IF(subreg % exec_type_size != 0 && subreg % exec_type_size != 1, "Destination subreg must be aligned to the size of the " @@ -1820,7 +1821,7 @@ special_requirements_for_handling_double_precision_data_types( */ if (is_double_precision && brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && - (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) { + (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) { ERROR_IF(!is_scalar_region && (src_stride % 8 != 0 || dst_stride % 8 != 0 || @@ -1845,7 +1846,7 @@ special_requirements_for_handling_double_precision_data_types( * We assume that the restriction applies to GLK as well. */ if (is_double_precision && - (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) { + (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) { ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == address_mode || BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == dst_address_mode, "Indirect addressing is not allowed when the execution type " @@ -1862,7 +1863,8 @@ special_requirements_for_handling_double_precision_data_types( * We assume that the restriction does not apply to the null register. */ if (is_double_precision && - (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) { + (devinfo->platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(devinfo))) { ERROR_IF(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MAC || brw_inst_acc_wr_control(devinfo, inst) || (BRW_ARCHITECTURE_REGISTER_FILE == file && @@ -1949,7 +1951,7 @@ special_requirements_for_handling_double_precision_data_types( * We assume that the restriction applies to GLK as well. */ if (is_double_precision && - (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) { + (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) { ERROR_IF(brw_inst_no_dd_check(devinfo, inst) || brw_inst_no_dd_clear(devinfo, inst), "DepCtrl is not allowed when the execution type is 64-bit"); diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 728ad8865b2..51ab3c4b119 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -3829,7 +3829,7 @@ fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_ins void fs_visitor::insert_gfx4_send_dependency_workarounds() { - if (devinfo->ver != 4 || devinfo->is_g4x) + if (devinfo->ver != 4 || devinfo->platform == INTEL_PLATFORM_G4X) return; bool progress = false; @@ -7105,7 +7105,7 @@ get_fpu_lowered_simd_width(const struct intel_device_info *devinfo, for (unsigned i = 0; i < inst->sources; i++) { /* IVB implements DF scalars as <0;2,1> regions. */ const bool is_scalar_exception = is_uniform(inst->src[i]) && - (devinfo->is_haswell || type_sz(inst->src[i].type) != 8); + (devinfo->platform == INTEL_PLATFORM_HSW || type_sz(inst->src[i].type) != 8); const bool is_packed_word_exception = type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 && type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1; @@ -7384,7 +7384,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo, * should * "Force BFI instructions to be executed always in SIMD8." */ - return MIN2(devinfo->is_haswell ? 8 : ~0u, + return MIN2(devinfo->platform == INTEL_PLATFORM_HSW ? 8 : ~0u, get_fpu_lowered_simd_width(devinfo, inst)); case BRW_OPCODE_IF: @@ -7401,7 +7401,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo, /* Unary extended math instructions are limited to SIMD8 on Gfx4 and * Gfx6. Extended Math Function is limited to SIMD8 with half-float. */ - if (devinfo->ver == 6 || (devinfo->ver == 4 && !devinfo->is_g4x)) + if (devinfo->ver == 6 || devinfo->verx10 == 40) return MIN2(8, inst->exec_size); if (inst->dst.type == BRW_REGISTER_TYPE_HF) return MIN2(8, inst->exec_size); @@ -8937,7 +8937,7 @@ fs_visitor::allocate_registers(bool allow_spilling) prog_data->total_scratch = brw_get_scratch_size(last_scratch); if (stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) { - if (devinfo->is_haswell) { + if (devinfo->platform == INTEL_PLATFORM_HSW) { /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space" * field documentation, Haswell supports a minimum of 2kB of * scratch space for compute shaders, unlike every other stage @@ -9328,7 +9328,7 @@ fs_visitor::run_cs(bool allow_spilling) if (shader_time_index >= 0) emit_shader_time_begin(); - if (devinfo->is_haswell && prog_data->total_shared > 0) { + if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) { /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */ const fs_builder abld = bld.exec_all().group(1, 0); abld.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW), diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index a1a74d14a78..8f59e4113d0 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -279,7 +279,7 @@ fs_generator::patch_halt_jumps() brw_inst_set_thread_control(devinfo, reset, BRW_THREAD_SWITCH); } - if (devinfo->ver == 4 && !devinfo->is_g4x) { + if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X) { /* From the g965 PRM: * * "[DevBW, DevCL] Erratum: The subfields in mask stack register are @@ -550,7 +550,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst, if (type_sz(reg.type) > 4 && ((devinfo->verx10 == 70) || - devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) || + devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_float || devinfo->verx10 >= 125)) { /* IVB has an issue (which we found empirically) where it reads two * address register components per channel for indirectly addressed @@ -715,7 +715,7 @@ fs_generator::generate_shuffle(fs_inst *inst, if (type_sz(src.type) > 4 && ((devinfo->verx10 == 70) || - devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) || + devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_float)) { /* IVB has an issue (which we found empirically) where it reads * two address register components per channel for indirectly @@ -1418,7 +1418,7 @@ fs_generator::generate_ddy(const fs_inst *inst, * inherits its FP16 hardware from SKL, so it is not affected. */ if (devinfo->ver >= 11 || - (devinfo->is_broadwell && src.type == BRW_REGISTER_TYPE_HF)) { + (devinfo->platform == INTEL_PLATFORM_BDW && src.type == BRW_REGISTER_TYPE_HF)) { src = stride(src, 0, 2, 1); brw_push_insn_state(p); @@ -2285,7 +2285,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, src[0], brw_null_reg()); } else { assert(inst->mlen >= 1); - assert(devinfo->ver == 5 || devinfo->is_g4x || inst->exec_size == 8); + assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X || inst->exec_size == 8); gfx4_math(p, dst, brw_math_function(inst->opcode), inst->base_mrf, src[0], @@ -2583,7 +2583,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, struct brw_reg strided = stride(suboffset(src[0], component), vstride, width, 0); if (type_sz(src[0].type) > 4 && - (devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) || + (devinfo->platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_float)) { /* IVB has an issue (which we found empirically) where it reads * two address register components per channel for indirectly @@ -2661,7 +2662,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; case BRW_OPCODE_DIM: - assert(devinfo->is_haswell); + assert(devinfo->platform == INTEL_PLATFORM_HSW); assert(src[0].type == BRW_REGISTER_TYPE_DF); assert(dst.type == BRW_REGISTER_TYPE_DF); brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F)); diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp b/src/intel/compiler/brw_fs_lower_regioning.cpp index c9ce2a814db..c1ff057064a 100644 --- a/src/intel/compiler/brw_fs_lower_regioning.cpp +++ b/src/intel/compiler/brw_fs_lower_regioning.cpp @@ -203,7 +203,8 @@ namespace { case SHADER_OPCODE_BROADCAST: case SHADER_OPCODE_MOV_INDIRECT: return (((devinfo->verx10 == 70) || - devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) || + devinfo->platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(devinfo) || devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) || (devinfo->verx10 >= 125 && brw_reg_type_is_floating_point(inst->src[0].type)) ? diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5ba9473684e..1d533d233df 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4658,7 +4658,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr (instr->num_components - 1) * type_sz(dest.type); bool supports_64bit_indirects = - !devinfo->is_cherryview && !intel_device_info_is_9lp(devinfo); + devinfo->platform != INTEL_PLATFORM_CHV && !intel_device_info_is_9lp(devinfo); if (type_sz(dest.type) != 8 || supports_64bit_indirects) { for (unsigned j = 0; j < instr->num_components; j++) { @@ -6467,7 +6467,7 @@ setup_imm_df(const fs_builder &bld, double v) /* gfx7.5 does not support DF immediates straighforward but the DIM * instruction allows to set the 64-bit immediate value. */ - if (devinfo->is_haswell) { + if (devinfo->platform == INTEL_PLATFORM_HSW) { const fs_builder ubld = bld.exec_all().group(1, 0); fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1); ubld.DIM(dst, brw_imm_df(v)); diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 2a9e3fbd642..5b531f4f805 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -93,7 +93,7 @@ brw_inst_##name(const struct intel_device_info *devinfo, \ high = hi6; low = lo6; \ } else if (devinfo->ver >= 5) { \ high = hi5; low = lo5; \ - } else if (devinfo->is_g4x) { \ + } else if (devinfo->verx10 >= 45) { \ high = hi45; low = lo45; \ } else { \ high = hi4; low = lo4; \ @@ -299,7 +299,8 @@ F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30) F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 8) FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 6) -FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5) +FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->verx10 == 45 || + devinfo->ver == 5) F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92) FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->ver >= 6) F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16) @@ -916,7 +917,7 @@ FF(sampler_msg_type, /* 7: */ MD(16), MD(12), /* 8: */ MD(16), MD(12), /* 12: */ MD12(16), MD12(12)) -FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->ver == 4 && !devinfo->is_g4x) +FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->verx10 == 40) FD(sampler, /* 4: */ MD(11), MD(8), /* 4.5: */ MD(11), MD(8), @@ -1395,7 +1396,7 @@ F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_i FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver <= 6) F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */ FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->ver >= 6) -FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5) +FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->verx10 == 45 || devinfo->ver == 5) F(subreg_index, /* 4+ */ 22, 18, /* 12+ */ 39, 35) F(datatype_index, /* 4+ */ 17, 13, /* 12+ */ 34, 30) F(control_index, /* 4+ */ 12, 8, /* 12+ */ 28, 24) diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h index a61e66303b6..6f7bab25272 100644 --- a/src/intel/compiler/brw_ir_fs.h +++ b/src/intel/compiler/brw_ir_fs.h @@ -570,7 +570,8 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo, if (type_sz(dst_type) > 4 || type_sz(exec_type) > 4 || (type_sz(exec_type) == 4 && is_dword_multiply)) - return devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) || + return devinfo->platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(devinfo) || devinfo->verx10 >= 125; else if (brw_reg_type_is_floating_point(dst_type)) diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp index 2a7dc787afe..e3af579c8dd 100644 --- a/src/intel/compiler/brw_ir_performance.cpp +++ b/src/intel/compiler/brw_ir_performance.cpp @@ -367,7 +367,7 @@ namespace { else return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 8, 4, 12, 0, 0); - } else if (devinfo->is_haswell) { + } else if (devinfo->verx10 >= 75) { return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 10, 6 /* XXX */, 16, 0, 0); } else { @@ -392,7 +392,7 @@ namespace { else return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 8, 4, 12, 0, 0); - } else if (devinfo->is_haswell) { + } else if (devinfo->verx10 >= 75) { if (info.tx == BRW_REGISTER_TYPE_F) return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 12, 8 /* XXX */, 18, 0, 0); @@ -422,7 +422,7 @@ namespace { else if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2, 0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2, 0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0); else if (devinfo->ver >= 7) @@ -442,7 +442,7 @@ namespace { else return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2, 0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0); - } else if (devinfo->is_haswell) { + } else if (devinfo->verx10 >= 75) { if (info.tx == BRW_REGISTER_TYPE_F) return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2, 0, 12, 8 /* XXX */, 18, 0, 0); @@ -472,7 +472,7 @@ namespace { else if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4, 0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4, 0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0); else if (devinfo->ver >= 7) @@ -488,7 +488,7 @@ namespace { if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0); else @@ -524,7 +524,7 @@ namespace { if (devinfo->ver >= 8) return calculate_desc(info, unit_em, -2, 4, 0, 0, 4, 0, 16, 0, 0, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_em, 0, 2, 0, 0, 2, 0, 12, 0, 0, 0, 0); else @@ -535,7 +535,7 @@ namespace { if (devinfo->ver >= 8) return calculate_desc(info, unit_em, -2, 4, 0, 0, 8, 0, 24, 0, 0, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_em, 0, 2, 0, 0, 4, 0, 20, 0, 0, 0, 0); else @@ -603,7 +603,7 @@ namespace { if (devinfo->ver >= 8) return calculate_desc(info, unit_null, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_null, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); else @@ -614,7 +614,7 @@ namespace { if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 0, 4, 0, 0, 4, 0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0); else @@ -625,7 +625,7 @@ namespace { if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 0, 4, 1, 0, 4, 0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0, 2, 1, 0, 2, 0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0); else if (devinfo->ver >= 6) @@ -643,7 +643,7 @@ namespace { return calculate_desc(info, unit_fpu, 16, 6, 0, 0, 6, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 20, 6, 0, 0, 6, 0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */, 0, 0); @@ -663,7 +663,7 @@ namespace { return calculate_desc(info, unit_fpu, 34, 0, 0, 34, 0, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 34, 0, 0, 34, 0, 0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */, 0, 0); @@ -679,7 +679,7 @@ namespace { else if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 18, 0, 0, 4, 0, 0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 18, 0, 0, 4, 0, 0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0); else if (devinfo->ver >= 7) @@ -695,7 +695,7 @@ namespace { else if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 2, 0, 0, 2, 0, 0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 36, 0, 0, 6, 0, 0, 10, 6 /* XXX */, 16 /* XXX */, 0, 0); else if (devinfo->ver >= 7) @@ -714,7 +714,7 @@ namespace { return calculate_desc(info, unit_fpu, 20 /* XXX */, 0, 0, 4 /* XXX */, 0, 0, 0, 0, 0, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 24 /* XXX */, 0, 0, 4 /* XXX */, 0, 0, 0, 0, 0, 0, 0); @@ -736,7 +736,7 @@ namespace { 42 /* XXX */, 0, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0, 44 /* XXX */, 0, 0, 44 /* XXX */, 0, 10 /* XXX */, 6 /* XXX */, @@ -760,7 +760,7 @@ namespace { 0, 4 /* XXX */, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 10 /* XXX */, 4 /* XXX */, 0, 0, 4 /* XXX */, 0, 10 /* XXX */, 6 /* XXX */, @@ -782,7 +782,7 @@ namespace { 0, 8 /* XXX */, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0 /* XXX */, 8 /* XXX */, 0, 0, 8 /* XXX */, 0, 10 /* XXX */, 6 /* XXX */, @@ -800,7 +800,7 @@ namespace { else if (devinfo->ver >= 8) return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 0, 2, 0, 0, 2, 0, 12, 8 /* XXX */, 18 /* XXX */, 0, 0); else @@ -825,7 +825,7 @@ namespace { 4 /* XXX */, 0, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 4 /* XXX */, 0, 0, 4 /* XXX */, 0, 0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */, @@ -846,7 +846,7 @@ namespace { 6 /* XXX */, 0, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 26 /* XXX */, 0, 0, 6 /* XXX */, 0, 0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */, @@ -864,7 +864,7 @@ namespace { 8 /* XXX */, 0, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 38 /* XXX */, 0, 0, 8 /* XXX */, 0, 0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */, @@ -883,7 +883,7 @@ namespace { 4 /* XXX */, 0, 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) return calculate_desc(info, unit_fpu, 14 /* XXX */, 0, 0, 4 /* XXX */, 0, 0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */, diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 1d69eebc852..d50feb093bb 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -775,7 +775,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, /* See also brw_nir_trig_workarounds.py */ if (compiler->precise_trig && - !(devinfo->ver >= 10 || devinfo->is_kabylake)) + !(devinfo->ver >= 10 || devinfo->platform == INTEL_PLATFORM_KBL)) OPT(brw_nir_apply_trig_workarounds); if (devinfo->ver >= 12) diff --git a/src/intel/compiler/brw_nir_lower_storage_image.c b/src/intel/compiler/brw_nir_lower_storage_image.c index a9946694f3b..57f553c4ac6 100644 --- a/src/intel/compiler/brw_nir_lower_storage_image.c +++ b/src/intel/compiler/brw_nir_lower_storage_image.c @@ -200,7 +200,7 @@ image_address(nir_builder *b, const struct intel_device_info *devinfo, /* Multiply by the Bpp value. */ addr = nir_imul(b, idx, nir_channel(b, stride, 0)); - if (devinfo->ver < 8 && !devinfo->is_baytrail) { + if (devinfo->ver < 8 && devinfo->platform != INTEL_PLATFORM_BYT) { /* Take into account the two dynamically specified shifts. Both are * used to implement swizzling of X-tiled surfaces. For Y-tiled * surfaces only one bit needs to be XOR-ed with bit 6 of the memory diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index ae24bff2271..5efea03e04a 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -975,7 +975,7 @@ schedule_node::schedule_node(backend_instruction *inst, if (!sched->post_reg_alloc) this->latency = 1; else if (devinfo->ver >= 6) - set_latency_gfx7(devinfo->is_haswell); + set_latency_gfx7(devinfo->verx10 == 75); else set_latency_gfx4(); } diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index 5f880951e68..7ade12344ec 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -130,7 +130,7 @@ generate_tex(struct brw_codegen *p, case SHADER_OPCODE_TXD: if (inst->shadow_compare) { /* Gfx7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */ - assert(devinfo->is_haswell); + assert(devinfo->verx10 == 75); msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; } else { msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS; @@ -738,7 +738,8 @@ static void generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst) { const struct intel_device_info *devinfo = p->devinfo; - const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail; + const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB || + devinfo->platform == INTEL_PLATFORM_BYT; /* "Instance Count" comes as part of the payload in r0.2 bits 23:17. * @@ -1058,7 +1059,8 @@ generate_tcs_create_barrier_header(struct brw_codegen *p, struct brw_reg dst) { const struct intel_device_info *devinfo = p->devinfo; - const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail; + const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB || + devinfo->platform == INTEL_PLATFORM_BYT; struct brw_reg m0_2 = get_element_ud(dst, 2); unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances; @@ -1158,7 +1160,7 @@ generate_scratch_read(struct brw_codegen *p, if (devinfo->ver >= 6) msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; - else if (devinfo->ver == 5 || devinfo->is_g4x) + else if (devinfo->verx10 >= 45) msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; else msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; @@ -1301,7 +1303,7 @@ generate_pull_constant_load(struct brw_codegen *p, if (devinfo->ver >= 6) msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; - else if (devinfo->ver == 5 || devinfo->is_g4x) + else if (devinfo->verx10 >= 45) msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; else msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; @@ -2188,7 +2190,7 @@ generate_code(struct brw_codegen *p, break; case BRW_OPCODE_DIM: - assert(devinfo->is_haswell); + assert(devinfo->verx10 == 75); assert(src[0].type == BRW_REGISTER_TYPE_DF); assert(dst.type == BRW_REGISTER_TYPE_DF); brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F)); diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 435f79dad59..4600368194d 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -288,7 +288,7 @@ setup_imm_df(const vec4_builder &bld, double v) /* gfx7.5 does not support DF immediates straighforward but the DIM * instruction allows to set the 64-bit immediate value. */ - if (devinfo->is_haswell) { + if (devinfo->verx10 == 75) { const vec4_builder ubld = bld.exec_all(); const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_DF); ubld.DIM(dst, brw_imm_df(v)); diff --git a/src/intel/compiler/brw_vec4_surface_builder.cpp b/src/intel/compiler/brw_vec4_surface_builder.cpp index 5418f600545..fce3133bef8 100644 --- a/src/intel/compiler/brw_vec4_surface_builder.cpp +++ b/src/intel/compiler/brw_vec4_surface_builder.cpp @@ -163,7 +163,7 @@ namespace brw { unsigned dims, unsigned size, brw_predicate pred) { - const bool has_simd4x2 = bld.shader->devinfo->is_haswell; + const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75; emit_send(bld, VEC4_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(), emit_insert(bld, addr, dims, has_simd4x2), has_simd4x2 ? 1 : dims, @@ -184,7 +184,7 @@ namespace brw { unsigned dims, unsigned rsize, unsigned op, brw_predicate pred) { - const bool has_simd4x2 = bld.shader->devinfo->is_haswell; + const bool has_simd4x2 = bld.shader->devinfo->verx10 == 75; /* Zip the components of both sources, they are represented as the X * and Y components of the same vector. diff --git a/src/intel/compiler/brw_vec4_visitor.cpp b/src/intel/compiler/brw_vec4_visitor.cpp index a10f545d5b1..3ad8868ac5f 100644 --- a/src/intel/compiler/brw_vec4_visitor.cpp +++ b/src/intel/compiler/brw_vec4_visitor.cpp @@ -819,7 +819,7 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type, bool vec4_visitor::is_high_sampler(src_reg sampler) { - if (!devinfo->is_haswell) + if (devinfo->verx10 != 75) return false; return sampler.file != IMM || sampler.ud >= 16; diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp index a7d5e919ce8..16e2e4c6100 100644 --- a/src/intel/compiler/test_eu_compact.cpp +++ b/src/intel/compiler/test_eu_compact.cpp @@ -99,7 +99,7 @@ clear_pad_bits(const struct intel_device_info *devinfo, brw_inst *inst) brw_inst_set_bits(inst, 127, 111, 0); } - if (devinfo->ver == 8 && !devinfo->is_cherryview && + if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV && is_3src(devinfo, brw_inst_opcode(devinfo, inst))) { brw_inst_set_bits(inst, 105, 105, 0); brw_inst_set_bits(inst, 84, 84, 0); @@ -119,7 +119,7 @@ skip_bit(const struct intel_device_info *devinfo, brw_inst *src, int bit) return true; if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) { - if (devinfo->ver >= 9 || devinfo->is_cherryview) { + if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) { if (bit == 127) return true; } else { diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index 6c267d96b5f..ac1cad0d563 100644 --- a/src/intel/compiler/test_eu_validate.cpp +++ b/src/intel/compiler/test_eu_validate.cpp @@ -1234,7 +1234,7 @@ TEST_P(validation_test, byte_destination_relaxed_alignment) brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2); brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 1); - if (devinfo.ver > 4 || devinfo.is_g4x) { + if (devinfo.verx10 >= 45) { EXPECT_TRUE(validate(p)); } else { EXPECT_FALSE(validate(p)); @@ -1416,7 +1416,7 @@ TEST_P(validation_test, half_float_conversion) brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1); } - if (devinfo.is_cherryview || devinfo.ver >= 9) + if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9) EXPECT_EQ(inst[i].expected_result_chv_gfx9, validate(p)); else EXPECT_EQ(inst[i].expected_result_bdw, validate(p)); @@ -1603,7 +1603,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0) brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr); - if (devinfo.is_cherryview || devinfo.ver >= 9) + if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9) EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p)); else EXPECT_EQ(inst[i].expected_result_bdw, validate(p)); @@ -1686,7 +1686,7 @@ TEST_P(validation_test, mixed_float_fp16_dest_with_acc) brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride); - if (devinfo.is_cherryview || devinfo.ver >= 9) + if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9) EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p)); else EXPECT_EQ(inst[i].expected_result_bdw, validate(p)); @@ -1830,7 +1830,7 @@ TEST_P(validation_test, mixed_float_align1_packed_fp16_dst) brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size); - if (devinfo.is_cherryview || devinfo.ver >= 9) + if (devinfo.platform == INTEL_PLATFORM_CHV || devinfo.ver >= 9) EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p)); else EXPECT_EQ(inst[i].expected_result_bdw, validate(p)); @@ -2312,7 +2312,8 @@ TEST_P(validation_test, qword_low_power_align1_regioning_restrictions) brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); - if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) { + if (devinfo.platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(&devinfo)) { EXPECT_EQ(inst[i].expected_result, validate(p)); } else { EXPECT_TRUE(validate(p)); @@ -2444,7 +2445,8 @@ TEST_P(validation_test, qword_low_power_no_indirect_addressing) brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); - if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) { + if (devinfo.platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(&devinfo)) { EXPECT_EQ(inst[i].expected_result, validate(p)); } else { EXPECT_TRUE(validate(p)); @@ -2591,7 +2593,8 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width); brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride); - if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) { + if (devinfo.platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(&devinfo)) { EXPECT_EQ(inst[i].expected_result, validate(p)); } else { EXPECT_TRUE(validate(p)); @@ -2607,7 +2610,8 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf) brw_MAC(p, retype(g0, BRW_REGISTER_TYPE_DF), retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF), retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF)); - if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) { + if (devinfo.platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(&devinfo)) { EXPECT_FALSE(validate(p)); } else { EXPECT_TRUE(validate(p)); @@ -2809,7 +2813,8 @@ TEST_P(validation_test, qword_low_power_no_depctrl) brw_inst_set_no_dd_check(&devinfo, last_inst, inst[i].no_dd_check); brw_inst_set_no_dd_clear(&devinfo, last_inst, inst[i].no_dd_clear); - if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) { + if (devinfo.platform == INTEL_PLATFORM_CHV || + intel_device_info_is_9lp(&devinfo)) { EXPECT_EQ(inst[i].expected_result, validate(p)); } else { EXPECT_TRUE(validate(p)); diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c index 06e42bcc8d8..a72eba883b6 100644 --- a/src/intel/dev/intel_device_info.c +++ b/src/intel/dev/intel_device_info.c @@ -86,12 +86,14 @@ intel_device_name_to_pci_device_id(const char *name) static const struct intel_device_info intel_device_info_gfx3 = { .ver = 3, + .platform = INTEL_PLATFORM_GFX3, .simulator_id = -1, .cs_prefetch_size = 512, }; static const struct intel_device_info intel_device_info_i965 = { .ver = 4, + .platform = INTEL_PLATFORM_I965, .has_negative_rhw_bug = true, .num_slices = 1, .num_subslices = { 1, }, @@ -114,7 +116,7 @@ static const struct intel_device_info intel_device_info_g4x = { .has_pln = true, .has_compr4 = true, .has_surface_tile_offset = true, - .is_g4x = true, + .platform = INTEL_PLATFORM_G4X, .num_slices = 1, .num_subslices = { 1, }, .num_eu_per_subslice = 10, @@ -132,6 +134,7 @@ static const struct intel_device_info intel_device_info_g4x = { static const struct intel_device_info intel_device_info_ilk = { .ver = 5, + .platform = INTEL_PLATFORM_ILK, .has_pln = true, .has_compr4 = true, .has_surface_tile_offset = true, @@ -153,6 +156,7 @@ static const struct intel_device_info intel_device_info_ilk = { static const struct intel_device_info intel_device_info_snb_gt1 = { .ver = 6, .gt = 1, + .platform = INTEL_PLATFORM_SNB, .has_hiz_and_separate_stencil = true, .has_llc = true, .has_pln = true, @@ -183,6 +187,7 @@ static const struct intel_device_info intel_device_info_snb_gt1 = { static const struct intel_device_info intel_device_info_snb_gt2 = { .ver = 6, .gt = 2, + .platform = INTEL_PLATFORM_SNB, .has_hiz_and_separate_stencil = true, .has_llc = true, .has_pln = true, @@ -223,7 +228,7 @@ static const struct intel_device_info intel_device_info_snb_gt2 = { .cs_prefetch_size = 512 static const struct intel_device_info intel_device_info_ivb_gt1 = { - GFX7_FEATURES, .is_ivybridge = true, .gt = 1, + GFX7_FEATURES, .platform = INTEL_PLATFORM_IVB, .gt = 1, .num_slices = 1, .num_subslices = { 1, }, .num_eu_per_subslice = 6, @@ -251,7 +256,7 @@ static const struct intel_device_info intel_device_info_ivb_gt1 = { }; static const struct intel_device_info intel_device_info_ivb_gt2 = { - GFX7_FEATURES, .is_ivybridge = true, .gt = 2, + GFX7_FEATURES, .platform = INTEL_PLATFORM_IVB, .gt = 2, .num_slices = 1, .num_subslices = { 1, }, .num_eu_per_subslice = 12, @@ -280,7 +285,7 @@ static const struct intel_device_info intel_device_info_ivb_gt2 = { }; static const struct intel_device_info intel_device_info_byt = { - GFX7_FEATURES, .is_baytrail = true, .gt = 1, + GFX7_FEATURES, .platform = INTEL_PLATFORM_BYT, .gt = 1, .num_slices = 1, .num_subslices = { 1, }, .num_eu_per_subslice = 4, @@ -308,10 +313,10 @@ static const struct intel_device_info intel_device_info_byt = { .simulator_id = 10, }; -#define HSW_FEATURES \ - GFX7_FEATURES, \ - .is_haswell = true, \ - .verx10 = 75, \ +#define HSW_FEATURES \ + GFX7_FEATURES, \ + .platform = INTEL_PLATFORM_HSW, \ + .verx10 = 75, \ .supports_simd16_3src = true static const struct intel_device_info intel_device_info_hsw_gt1 = { @@ -426,7 +431,7 @@ static const struct intel_device_info intel_device_info_hsw_gt3 = { static const struct intel_device_info intel_device_info_bdw_gt1 = { GFX8_FEATURES, .gt = 1, - .is_broadwell = true, + .platform = INTEL_PLATFORM_BDW, .num_slices = 1, .num_subslices = { 2, }, .num_eu_per_subslice = 6, @@ -450,7 +455,7 @@ static const struct intel_device_info intel_device_info_bdw_gt1 = { static const struct intel_device_info intel_device_info_bdw_gt2 = { GFX8_FEATURES, .gt = 2, - .is_broadwell = true, + .platform = INTEL_PLATFORM_BDW, .num_slices = 1, .num_subslices = { 3, }, .num_eu_per_subslice = 8, @@ -473,7 +478,7 @@ static const struct intel_device_info intel_device_info_bdw_gt2 = { static const struct intel_device_info intel_device_info_bdw_gt3 = { GFX8_FEATURES, .gt = 3, - .is_broadwell = true, + .platform = INTEL_PLATFORM_BDW, .num_slices = 2, .num_subslices = { 3, 3, }, .num_eu_per_subslice = 8, @@ -495,7 +500,7 @@ static const struct intel_device_info intel_device_info_bdw_gt3 = { }; static const struct intel_device_info intel_device_info_chv = { - GFX8_FEATURES, .is_cherryview = 1, .gt = 1, + GFX8_FEATURES, .platform = INTEL_PLATFORM_CHV, .gt = 1, .has_llc = false, .has_integer_dword_mul = false, .num_slices = 1, @@ -607,7 +612,7 @@ static const struct intel_device_info intel_device_info_chv = { static const struct intel_device_info intel_device_info_skl_gt1 = { GFX9_FEATURES, .gt = 1, - .is_skylake = true, + .platform = INTEL_PLATFORM_SKL, .num_slices = 1, .num_subslices = { 2, }, .num_eu_per_subslice = 6, @@ -621,7 +626,7 @@ static const struct intel_device_info intel_device_info_skl_gt1 = { static const struct intel_device_info intel_device_info_skl_gt2 = { GFX9_FEATURES, .gt = 2, - .is_skylake = true, + .platform = INTEL_PLATFORM_SKL, .num_slices = 1, .num_subslices = { 3, }, .num_eu_per_subslice = 8, @@ -631,7 +636,7 @@ static const struct intel_device_info intel_device_info_skl_gt2 = { static const struct intel_device_info intel_device_info_skl_gt3 = { GFX9_FEATURES, .gt = 3, - .is_skylake = true, + .platform = INTEL_PLATFORM_SKL, .num_slices = 2, .num_subslices = { 3, 3, }, .num_eu_per_subslice = 8, @@ -641,7 +646,7 @@ static const struct intel_device_info intel_device_info_skl_gt3 = { static const struct intel_device_info intel_device_info_skl_gt4 = { GFX9_FEATURES, .gt = 4, - .is_skylake = true, + .platform = INTEL_PLATFORM_SKL, .num_slices = 3, .num_subslices = { 3, 3, 3, }, .num_eu_per_subslice = 8, @@ -659,14 +664,14 @@ static const struct intel_device_info intel_device_info_skl_gt4 = { static const struct intel_device_info intel_device_info_bxt = { GFX9_LP_FEATURES_3X6, - .is_broxton = true, + .platform = INTEL_PLATFORM_BXT, .l3_banks = 2, .simulator_id = 14, }; static const struct intel_device_info intel_device_info_bxt_2x6 = { GFX9_LP_FEATURES_2X6, - .is_broxton = true, + .platform = INTEL_PLATFORM_BXT, .l3_banks = 1, .simulator_id = 14, }; @@ -677,7 +682,7 @@ static const struct intel_device_info intel_device_info_bxt_2x6 = { static const struct intel_device_info intel_device_info_kbl_gt1 = { GFX9_FEATURES, - .is_kabylake = true, + .platform = INTEL_PLATFORM_KBL, .gt = 1, .max_cs_threads = 7 * 6, @@ -695,7 +700,7 @@ static const struct intel_device_info intel_device_info_kbl_gt1 = { static const struct intel_device_info intel_device_info_kbl_gt1_5 = { GFX9_FEATURES, - .is_kabylake = true, + .platform = INTEL_PLATFORM_KBL, .gt = 1, .max_cs_threads = 7 * 6, @@ -708,7 +713,7 @@ static const struct intel_device_info intel_device_info_kbl_gt1_5 = { static const struct intel_device_info intel_device_info_kbl_gt2 = { GFX9_FEATURES, - .is_kabylake = true, + .platform = INTEL_PLATFORM_KBL, .gt = 2, .num_slices = 1, @@ -720,7 +725,7 @@ static const struct intel_device_info intel_device_info_kbl_gt2 = { static const struct intel_device_info intel_device_info_kbl_gt3 = { GFX9_FEATURES, - .is_kabylake = true, + .platform = INTEL_PLATFORM_KBL, .gt = 3, .num_slices = 2, @@ -732,7 +737,7 @@ static const struct intel_device_info intel_device_info_kbl_gt3 = { static const struct intel_device_info intel_device_info_kbl_gt4 = { GFX9_FEATURES, - .is_kabylake = true, + .platform = INTEL_PLATFORM_KBL, .gt = 4, /* @@ -754,21 +759,21 @@ static const struct intel_device_info intel_device_info_kbl_gt4 = { static const struct intel_device_info intel_device_info_glk = { GFX9_LP_FEATURES_3X6, - .is_geminilake = true, + .platform = INTEL_PLATFORM_GLK, .l3_banks = 2, .simulator_id = 17, }; static const struct intel_device_info intel_device_info_glk_2x6 = { GFX9_LP_FEATURES_2X6, - .is_geminilake = true, + .platform = INTEL_PLATFORM_GLK, .l3_banks = 2, .simulator_id = 17, }; static const struct intel_device_info intel_device_info_cfl_gt1 = { GFX9_FEATURES, - .is_coffeelake = true, + .platform = INTEL_PLATFORM_CFL, .gt = 1, .num_slices = 1, @@ -784,7 +789,7 @@ static const struct intel_device_info intel_device_info_cfl_gt1 = { }; static const struct intel_device_info intel_device_info_cfl_gt2 = { GFX9_FEATURES, - .is_coffeelake = true, + .platform = INTEL_PLATFORM_CFL, .gt = 2, .num_slices = 1, @@ -796,7 +801,7 @@ static const struct intel_device_info intel_device_info_cfl_gt2 = { static const struct intel_device_info intel_device_info_cfl_gt3 = { GFX9_FEATURES, - .is_coffeelake = true, + .platform = INTEL_PLATFORM_CFL, .gt = 3, .num_slices = 2, @@ -818,9 +823,10 @@ static const struct intel_device_info intel_device_info_cfl_gt3 = { .max_cs_threads = 56, \ .cs_prefetch_size = 512 -#define GFX11_FEATURES(_gt, _slices, _subslices, _l3) \ +#define GFX11_FEATURES(_gt, _slices, _subslices, _l3, _platform) \ GFX8_FEATURES, \ GFX11_HW_INFO, \ + .platform = _platform, \ .has_64bit_float = false, \ .has_64bit_int = false, \ .has_integer_dword_mul = false, \ @@ -842,7 +848,7 @@ static const struct intel_device_info intel_device_info_cfl_gt3 = { } static const struct intel_device_info intel_device_info_icl_gt2 = { - GFX11_FEATURES(2, 1, subslices(8), 8), + GFX11_FEATURES(2, 1, subslices(8), 8, INTEL_PLATFORM_ICL), .urb = { GFX11_URB_MIN_MAX_ENTRIES, }, @@ -850,7 +856,7 @@ static const struct intel_device_info intel_device_info_icl_gt2 = { }; static const struct intel_device_info intel_device_info_icl_gt1_5 = { - GFX11_FEATURES(1, 1, subslices(6), 6), + GFX11_FEATURES(1, 1, subslices(6), 6, INTEL_PLATFORM_ICL), .urb = { GFX11_URB_MIN_MAX_ENTRIES, }, @@ -858,7 +864,7 @@ static const struct intel_device_info intel_device_info_icl_gt1_5 = { }; static const struct intel_device_info intel_device_info_icl_gt1 = { - GFX11_FEATURES(1, 1, subslices(4), 6), + GFX11_FEATURES(1, 1, subslices(4), 6, INTEL_PLATFORM_ICL), .urb = { GFX11_URB_MIN_MAX_ENTRIES, }, @@ -866,7 +872,7 @@ static const struct intel_device_info intel_device_info_icl_gt1 = { }; static const struct intel_device_info intel_device_info_icl_gt0_5 = { - GFX11_FEATURES(1, 1, subslices(1), 6), + GFX11_FEATURES(1, 1, subslices(1), 6, INTEL_PLATFORM_ICL), .urb = { GFX11_URB_MIN_MAX_ENTRIES, }, @@ -874,7 +880,6 @@ static const struct intel_device_info intel_device_info_icl_gt0_5 = { }; #define GFX11_LP_FEATURES \ - .is_elkhartlake = true, \ .urb = { \ GFX11_URB_MIN_MAX_ENTRIES, \ }, \ @@ -882,35 +887,35 @@ static const struct intel_device_info intel_device_info_icl_gt0_5 = { .simulator_id = 28 static const struct intel_device_info intel_device_info_ehl_4x8 = { - GFX11_FEATURES(1, 1, subslices(4), 4), + GFX11_FEATURES(1, 1, subslices(4), 4, INTEL_PLATFORM_EHL), GFX11_LP_FEATURES, }; static const struct intel_device_info intel_device_info_ehl_4x6 = { - GFX11_FEATURES(1, 1, subslices(4), 4), + GFX11_FEATURES(1, 1, subslices(4), 4, INTEL_PLATFORM_EHL), GFX11_LP_FEATURES, .num_eu_per_subslice = 6, }; static const struct intel_device_info intel_device_info_ehl_4x5 = { - GFX11_FEATURES(1, 1, subslices(4), 4), + GFX11_FEATURES(1, 1, subslices(4), 4, INTEL_PLATFORM_EHL), GFX11_LP_FEATURES, .num_eu_per_subslice = 5, }; static const struct intel_device_info intel_device_info_ehl_4x4 = { - GFX11_FEATURES(1, 1, subslices(4), 4), + GFX11_FEATURES(1, 1, subslices(4), 4, INTEL_PLATFORM_EHL), GFX11_LP_FEATURES, .num_eu_per_subslice = 4, }; static const struct intel_device_info intel_device_info_ehl_2x8 = { - GFX11_FEATURES(1, 1, subslices(2), 4), + GFX11_FEATURES(1, 1, subslices(2), 4, INTEL_PLATFORM_EHL), GFX11_LP_FEATURES, }; static const struct intel_device_info intel_device_info_ehl_2x4 = { - GFX11_FEATURES(1, 1, subslices(2), 4), + GFX11_FEATURES(1, 1, subslices(2), 4, INTEL_PLATFORM_EHL), GFX11_LP_FEATURES, .num_eu_per_subslice =4, }; @@ -965,43 +970,43 @@ static const struct intel_device_info intel_device_info_ehl_2x4 = { static const struct intel_device_info intel_device_info_tgl_gt1 = { GFX12_GT_FEATURES(1), - .is_tigerlake = true, + .platform = INTEL_PLATFORM_TGL, }; static const struct intel_device_info intel_device_info_tgl_gt2 = { GFX12_GT_FEATURES(2), - .is_tigerlake = true, + .platform = INTEL_PLATFORM_TGL, }; static const struct intel_device_info intel_device_info_rkl_gt05 = { GFX12_GT05_FEATURES, - .is_rocketlake = true, + .platform = INTEL_PLATFORM_RKL, }; static const struct intel_device_info intel_device_info_rkl_gt1 = { GFX12_GT_FEATURES(1), - .is_rocketlake = true, + .platform = INTEL_PLATFORM_RKL, }; static const struct intel_device_info intel_device_info_adl_gt05 = { GFX12_GT05_FEATURES, - .is_alderlake = true, + .platform = INTEL_PLATFORM_ADL, }; static const struct intel_device_info intel_device_info_adl_gt1 = { GFX12_GT_FEATURES(1), - .is_alderlake = true, + .platform = INTEL_PLATFORM_ADL, }; static const struct intel_device_info intel_device_info_adl_gt2 = { GFX12_GT_FEATURES(2), - .is_alderlake = true, + .platform = INTEL_PLATFORM_ADL, .display_ver = 13, }; #define GFX12_DG1_SG1_FEATURES \ GFX12_GT_FEATURES(2), \ - .is_dg1 = true, \ + .platform = INTEL_PLATFORM_DG1, \ .has_llc = false, \ .has_local_mem = true, \ .urb.size = 768, \ @@ -1459,7 +1464,7 @@ has_get_tiling(int fd) static void fixup_chv_device_info(struct intel_device_info *devinfo) { - assert(devinfo->is_cherryview); + assert(devinfo->platform == INTEL_PLATFORM_CHV); /* Cherryview is annoying. The number of EUs is depending on fusing and * isn't determinable from the PCI ID alone. We default to the minimum @@ -1525,7 +1530,7 @@ init_max_scratch_ids(struct intel_device_info *devinfo) if (devinfo->verx10 == 125) subslices = 32; else if (devinfo->ver == 12) - subslices = (devinfo->is_dg1 || devinfo->gt == 2 ? 6 : 2); + subslices = (devinfo->platform == INTEL_PLATFORM_DG1 || devinfo->gt == 2 ? 6 : 2); else if (devinfo->ver == 11) subslices = 8; else if (devinfo->ver >= 9 && devinfo->ver < 11) @@ -1550,7 +1555,7 @@ init_max_scratch_ids(struct intel_device_info *devinfo) * allocated by the driver." */ scratch_ids_per_subslice = 8 * 8; - } else if (devinfo->is_haswell) { + } else if (devinfo->platform == INTEL_PLATFORM_HSW) { /* WaCSScratchSize:hsw * * Haswell's scratch space address calculation appears to be sparse @@ -1567,7 +1572,7 @@ init_max_scratch_ids(struct intel_device_info *devinfo) * number of threads per subslice. */ scratch_ids_per_subslice = 16 * 8; - } else if (devinfo->is_cherryview) { + } else if (devinfo->platform == INTEL_PLATFORM_CHV) { /* Cherryview devices have either 6 or 8 EUs per subslice, and each * EU has 7 threads. The 6 EU devices appear to calculate thread IDs * as if it had 8 EUs. @@ -1674,7 +1679,7 @@ intel_get_device_info_from_fd(int fd, struct intel_device_info *devinfo) getparam_topology(devinfo, fd); } - if (devinfo->is_cherryview) + if (devinfo->platform == INTEL_PLATFORM_CHV) fixup_chv_device_info(devinfo); /* Broadwell PRM says: diff --git a/src/intel/dev/intel_device_info.h b/src/intel/dev/intel_device_info.h index d5fc452e616..cdf499dc003 100644 --- a/src/intel/dev/intel_device_info.h +++ b/src/intel/dev/intel_device_info.h @@ -43,6 +43,31 @@ struct drm_i915_query_topology_info; #define INTEL_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gfx12 */ #define INTEL_DEVICE_MAX_PIXEL_PIPES (3) /* Maximum on gfx12 */ +enum intel_platform { + INTEL_PLATFORM_GFX3 = 1, + INTEL_PLATFORM_I965, + INTEL_PLATFORM_ILK, + INTEL_PLATFORM_G4X, + INTEL_PLATFORM_SNB, + INTEL_PLATFORM_IVB, + INTEL_PLATFORM_BYT, + INTEL_PLATFORM_HSW, + INTEL_PLATFORM_BDW, + INTEL_PLATFORM_CHV, + INTEL_PLATFORM_SKL, + INTEL_PLATFORM_BXT, + INTEL_PLATFORM_KBL, + INTEL_PLATFORM_GLK, + INTEL_PLATFORM_CFL, + INTEL_PLATFORM_ICL, + INTEL_PLATFORM_EHL, + INTEL_PLATFORM_TGL, + INTEL_PLATFORM_RKL, + INTEL_PLATFORM_DG1, + INTEL_PLATFORM_ADL, + INTEL_PLATFORM_DG2, +}; + /** * Intel hardware information and quirks */ @@ -55,23 +80,7 @@ struct intel_device_info int revision; int gt; - bool is_g4x; - bool is_ivybridge; - bool is_baytrail; - bool is_haswell; - bool is_broadwell; - bool is_cherryview; - bool is_skylake; - bool is_broxton; - bool is_kabylake; - bool is_geminilake; - bool is_coffeelake; - bool is_elkhartlake; - bool is_tigerlake; - bool is_rocketlake; - bool is_dg1; - bool is_alderlake; - bool is_dg2; + enum intel_platform platform; bool has_hiz_and_separate_stencil; bool must_use_separate_stencil; @@ -348,12 +357,14 @@ struct intel_device_info #ifdef GFX_VER #define intel_device_info_is_9lp(devinfo) \ - (GFX_VER == 9 && ((devinfo)->is_broxton || (devinfo)->is_geminilake)) + (GFX_VER == 9 && ((devinfo)->platform == INTEL_PLATFORM_BXT || \ + (devinfo)->platform == INTEL_PLATFORM_GLK)) #else #define intel_device_info_is_9lp(devinfo) \ - ((devinfo)->is_broxton || (devinfo)->is_geminilake) + ((devinfo)->platform == INTEL_PLATFORM_BXT || \ + (devinfo)->platform == INTEL_PLATFORM_GLK) #endif diff --git a/src/intel/dev/intel_device_info_test.c b/src/intel/dev/intel_device_info_test.c index db5feae0744..14a56558549 100644 --- a/src/intel/dev/intel_device_info_test.c +++ b/src/intel/dev/intel_device_info_test.c @@ -32,6 +32,8 @@ main(int argc, char *argv[]) assert(devinfo.ver < 7 || devinfo.max_constant_urb_size_kb > 0); + assert(devinfo.platform >= 1); + assert(devinfo.num_slices <= ARRAY_SIZE(devinfo.subslice_masks)); assert(devinfo.num_slices <= devinfo.max_slices); diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index d26d655ae28..1848659d344 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -99,11 +99,11 @@ static void isl_device_setup_mocs(struct isl_device *dev) { if (dev->info->ver >= 12) { - if (dev->info->is_dg2) { + if (dev->info->platform == INTEL_PLATFORM_DG2) { /* L3CC=WB; BSpec: 45101 */ dev->mocs.internal = 3 << 1; dev->mocs.external = 3 << 1; - } else if (dev->info->is_dg1) { + } else if (dev->info->platform == INTEL_PLATFORM_DG1) { /* L3CC=WB */ dev->mocs.internal = 5 << 1; /* Displayables on DG1 are free to cache in L3 since L3 is transient @@ -138,7 +138,7 @@ isl_device_setup_mocs(struct isl_device *dev) */ dev->mocs.internal = 0x78; } else if (dev->info->ver >= 7) { - if (dev->info->is_haswell) { + if (dev->info->platform == INTEL_PLATFORM_HSW) { /* MEMORY_OBJECT_CONTROL_STATE: * .LLCeLLCCacheabilityControlLLCCC = 0, * .L3CacheabilityControlL3CC = 1, @@ -170,7 +170,7 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage, if (external) return dev->mocs.external; - if (dev->info->ver >= 12 && !dev->info->is_dg1) { + if (dev->info->ver >= 12 && dev->info->platform != INTEL_PLATFORM_DG1) { if (usage & ISL_SURF_USAGE_STAGING_BIT) return dev->mocs.internal; @@ -929,7 +929,7 @@ isl_surf_choose_dim_layout(const struct isl_device *dev, * * The cube face textures are stored in the same way as 3D surfaces * are stored (see section 6.17.5 for details). For cube surfaces, - * however, the depth is equal to the number of faces (always 6) and + * however, the depth is equal to the number of faces (always 6) and * is not reduced for each MIP. */ if (ISL_GFX_VER(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT)) @@ -2126,7 +2126,7 @@ isl_surf_supports_ccs(const struct isl_device *dev, return false; /* Wa_22011186057: Disable compression on ADL-P A0 */ - if (dev->info->is_alderlake && dev->info->gt == 2 && + if (dev->info->platform == INTEL_PLATFORM_ADL && dev->info->gt == 2 && dev->info->revision == 0) return false; @@ -3198,7 +3198,7 @@ bool isl_swizzle_supports_rendering(const struct intel_device_info *devinfo, struct isl_swizzle swizzle) { - if (devinfo->is_haswell) { + if (devinfo->platform == INTEL_PLATFORM_HSW) { /* From the Haswell PRM, * RENDER_SURFACE_STATE::Shader Channel Select Red * diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 1b882cd02f2..32954baa133 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -71,7 +71,7 @@ struct brw_image_param; #endif #ifndef ISL_DEV_IS_G4X -#define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x) +#define ISL_DEV_IS_G4X(__dev) ((__dev)->info->platform == INTEL_PLATFORM_G4X) #endif #ifndef ISL_DEV_IS_HASWELL @@ -81,11 +81,11 @@ struct brw_image_param; * You can define this as a compile-time constant in the CFLAGS. For example, * `gcc -DISL_GFX_VER(dev)=9 ...`. */ -#define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell) +#define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_HSW) #endif #ifndef ISL_DEV_IS_BAYTRAIL -#define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail) +#define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_BYT) #endif #ifndef ISL_DEV_USE_SEPARATE_STENCIL @@ -2017,7 +2017,7 @@ isl_tiling_is_std_y(enum isl_tiling tiling) uint32_t isl_tiling_to_i915_tiling(enum isl_tiling tiling); -enum isl_tiling +enum isl_tiling isl_tiling_from_i915_tiling(uint32_t tiling); /** diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c index 321b857719a..0ad129868aa 100644 --- a/src/intel/isl/isl_format.c +++ b/src/intel/isl/isl_format.c @@ -713,14 +713,14 @@ isl_format_supports_sampling(const struct intel_device_info *devinfo, if (!format_info_exists(format)) return false; - if (devinfo->is_baytrail) { + if (devinfo->platform == INTEL_PLATFORM_BYT) { const struct isl_format_layout *fmtl = isl_format_get_layout(format); /* Support for ETC1 and ETC2 exists on Bay Trail even though big-core * GPUs didn't get it until Broadwell. */ if (fmtl->txc == ISL_TXC_ETC1 || fmtl->txc == ISL_TXC_ETC2) return true; - } else if (devinfo->is_cherryview) { + } else if (devinfo->platform == INTEL_PLATFORM_CHV) { /* Support for ASTC LDR theoretically exists on Cherry View even though * big-core GPUs didn't get it until Skylake. However, it's fairly * badly broken and requires some nasty workarounds which no Mesa driver @@ -774,7 +774,7 @@ isl_format_supports_vertex_fetch(const struct intel_device_info *devinfo, /* For vertex fetch, Bay Trail supports the same set of formats as Haswell * but is a superset of Ivy Bridge. */ - if (devinfo->is_baytrail) + if (devinfo->platform == INTEL_PLATFORM_BYT) return 75 >= format_info[format].input_vb; return devinfo->verx10 >= format_info[format].input_vb; @@ -849,7 +849,7 @@ isl_format_supports_ccs_e(const struct intel_device_info *devinfo, enum isl_format format) { /* Wa_22011186057: Disable compression on ADL-P A0 */ - if (devinfo->is_alderlake && devinfo->gt == 2 && devinfo->revision == 0) + if (devinfo->platform == INTEL_PLATFORM_ADL && devinfo->gt == 2 && devinfo->revision == 0) return false; if (!format_info_exists(format)) diff --git a/src/intel/isl/isl_gfx7.c b/src/intel/isl/isl_gfx7.c index e02045d7bb8..f3c55625606 100644 --- a/src/intel/isl/isl_gfx7.c +++ b/src/intel/isl/isl_gfx7.c @@ -324,7 +324,7 @@ isl_gfx6_filter_tiling(const struct isl_device *dev, if (info->width > 16382 && info->samples == 1 && info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT && (ISL_GFX_VER(dev) == 8 || - (dev->info->is_skylake && dev->info->gt != 4))) { + (dev->info->platform == INTEL_PLATFORM_SKL && dev->info->gt != 4))) { *flags &= ISL_TILING_LINEAR_BIT; } } diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index f6e7a48996e..aa946f123a0 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -760,7 +760,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * This bit must be set for the following surface types: BC2_UNORM * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM */ - if (GFX_VER >= 9 || dev->info->is_cherryview) { + if (GFX_VER >= 9 || dev->info->platform == INTEL_PLATFORM_CHV) { switch (info->view->format) { case ISL_FORMAT_BC2_UNORM: case ISL_FORMAT_BC3_UNORM: diff --git a/src/intel/perf/intel_perf.c b/src/intel/perf/intel_perf.c index a013e025ab3..231e32b218b 100644 --- a/src/intel/perf/intel_perf.c +++ b/src/intel/perf/intel_perf.c @@ -416,55 +416,56 @@ typedef void (*perf_register_oa_queries_t)(struct intel_perf_config *); static perf_register_oa_queries_t get_register_queries_function(const struct intel_device_info *devinfo) { - if (devinfo->is_haswell) + switch (devinfo->platform) { + case INTEL_PLATFORM_HSW: return intel_oa_register_queries_hsw; - if (devinfo->is_cherryview) + case INTEL_PLATFORM_CHV: return intel_oa_register_queries_chv; - if (devinfo->is_broadwell) + case INTEL_PLATFORM_BDW: return intel_oa_register_queries_bdw; - if (devinfo->is_broxton) + case INTEL_PLATFORM_BXT: return intel_oa_register_queries_bxt; - if (devinfo->is_skylake) { + case INTEL_PLATFORM_SKL: if (devinfo->gt == 2) return intel_oa_register_queries_sklgt2; if (devinfo->gt == 3) return intel_oa_register_queries_sklgt3; if (devinfo->gt == 4) return intel_oa_register_queries_sklgt4; - } - if (devinfo->is_kabylake) { + return NULL; + case INTEL_PLATFORM_KBL: if (devinfo->gt == 2) return intel_oa_register_queries_kblgt2; if (devinfo->gt == 3) return intel_oa_register_queries_kblgt3; - } - if (devinfo->is_geminilake) + return NULL; + case INTEL_PLATFORM_GLK: return intel_oa_register_queries_glk; - if (devinfo->is_coffeelake) { + case INTEL_PLATFORM_CFL: if (devinfo->gt == 2) return intel_oa_register_queries_cflgt2; if (devinfo->gt == 3) return intel_oa_register_queries_cflgt3; - } - if (devinfo->ver == 11) { - if (devinfo->is_elkhartlake) - return intel_oa_register_queries_ehl; + return NULL; + case INTEL_PLATFORM_ICL: return intel_oa_register_queries_icl; - } - if (devinfo->is_tigerlake) { + case INTEL_PLATFORM_EHL: + return intel_oa_register_queries_ehl; + case INTEL_PLATFORM_TGL: if (devinfo->gt == 1) return intel_oa_register_queries_tglgt1; if (devinfo->gt == 2) return intel_oa_register_queries_tglgt2; - } - if (devinfo->is_rocketlake) + return NULL; + case INTEL_PLATFORM_RKL: return intel_oa_register_queries_rkl; - if (devinfo->is_dg1) + case INTEL_PLATFORM_DG1: return intel_oa_register_queries_dg1; - if (devinfo->is_alderlake) + case INTEL_PLATFORM_ADL: return intel_oa_register_queries_adl; - - return NULL; + default: + return NULL; + } } static int @@ -549,7 +550,7 @@ load_pipeline_statistic_metrics(struct intel_perf_config *perf_cfg, intel_perf_query_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT, "N primitives leaving clipping"); - if (devinfo->is_haswell || devinfo->ver == 8) { + if (devinfo->verx10 == 75 || devinfo->ver == 8) { intel_perf_query_add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4, "N fragment shader invocations", "N fragment shader invocations"); @@ -713,7 +714,7 @@ oa_metrics_available(struct intel_perf_config *perf, int fd, /* If _paranoid == 1 then on Gfx8+ we won't be able to access OA * metrics unless running as root. */ - if (devinfo->is_haswell) + if (devinfo->platform == INTEL_PLATFORM_HSW) i915_perf_oa_available = true; else { uint64_t paranoid = 1; @@ -1311,7 +1312,7 @@ intel_perf_init_query_fields(struct intel_perf_config *perf_cfg, field->mask = PERF_CNT_VALUE_MASK; } - if (devinfo->ver == 8 && !devinfo->is_cherryview) { + if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV) { add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT, GFX7_RPSTAT1, 4, 0); diff --git a/src/intel/perf/intel_perf_mdapi.c b/src/intel/perf/intel_perf_mdapi.c index 6e06e7a2be1..02ee7340f50 100644 --- a/src/intel/perf/intel_perf_mdapi.c +++ b/src/intel/perf/intel_perf_mdapi.c @@ -44,7 +44,7 @@ intel_perf_query_result_write_mdapi(void *data, uint32_t data_size, if (data_size < sizeof(*mdapi_data)) return 0; - assert(devinfo->is_haswell); + assert(devinfo->platform == INTEL_PLATFORM_HSW); for (int i = 0; i < ARRAY_SIZE(mdapi_data->ACounters); i++) mdapi_data->ACounters[i] = result->accumulator[1 + i]; @@ -164,7 +164,7 @@ intel_perf_register_mdapi_statistic_query(struct intel_perf_config *perf_cfg, "N primitives entering clipping"); intel_perf_query_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT, "N primitives leaving clipping"); - if (devinfo->is_haswell || devinfo->ver == 8) { + if (devinfo->verx10 == 75 || devinfo->ver == 8) { intel_perf_query_add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4, "N fragment shader invocations", "N fragment shader invocations"); diff --git a/src/intel/tools/intel_dump_gpu.c b/src/intel/tools/intel_dump_gpu.c index b3162283f94..dc57a77ac88 100644 --- a/src/intel/tools/intel_dump_gpu.c +++ b/src/intel/tools/intel_dump_gpu.c @@ -563,7 +563,7 @@ ioctl(int fd, unsigned long request, ...) return 0; case I915_PARAM_HAS_EXEC_SOFTPIN: - *getparam->value = devinfo.ver >= 8 && !devinfo.is_cherryview; + *getparam->value = devinfo.ver >= 8 && devinfo.platform != INTEL_PLATFORM_CHV; return 0; default: @@ -582,9 +582,9 @@ ioctl(int fd, unsigned long request, ...) if (device_override) { switch (getparam->param) { case I915_CONTEXT_PARAM_GTT_SIZE: - if (devinfo.is_elkhartlake) + if (devinfo.platform == INTEL_PLATFORM_EHL) getparam->value = 1ull << 36; - else if (devinfo.ver >= 8 && !devinfo.is_cherryview) + else if (devinfo.ver >= 8 && devinfo.platform != INTEL_PLATFORM_CHV) getparam->value = 1ull << 48; else getparam->value = 1ull << 31; diff --git a/src/intel/tools/intel_noop_drm_shim.c b/src/intel/tools/intel_noop_drm_shim.c index 3c1d7a21dbe..9013c0df996 100644 --- a/src/intel/tools/intel_noop_drm_shim.c +++ b/src/intel/tools/intel_noop_drm_shim.c @@ -124,7 +124,7 @@ i915_ioctl_gem_context_getparam(int fd, unsigned long request, void *arg) struct drm_i915_gem_context_param *param = arg; if (param->param == I915_CONTEXT_PARAM_GTT_SIZE) { - if (i915.devinfo.ver >= 8 && !i915.devinfo.is_cherryview) + if (i915.devinfo.ver >= 8 && i915.devinfo.platform != INTEL_PLATFORM_CHV) param->value = 1ull << 48; else param->value = 1ull << 31; @@ -319,7 +319,7 @@ i915_gem_get_aperture(int fd, unsigned long request, void *arg) struct drm_i915_gem_get_aperture *aperture = arg; if (i915.devinfo.ver >= 8 && - !i915.devinfo.is_cherryview) { + i915.devinfo.platform != INTEL_PLATFORM_CHV) { aperture->aper_size = 1ull << 48; aperture->aper_available_size = 1ull << 48; } else { diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 5a9c96fe460..0c903deb6a8 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -772,11 +772,11 @@ anv_physical_device_try_create(struct anv_instance *instance, } bool is_alpha = true; - if (devinfo.is_haswell) { + if (devinfo.platform == INTEL_PLATFORM_HSW) { mesa_logw("Haswell Vulkan support is incomplete"); - } else if (devinfo.ver == 7 && !devinfo.is_baytrail) { + } else if (devinfo.platform == INTEL_PLATFORM_IVB) { mesa_logw("Ivy Bridge Vulkan support is incomplete"); - } else if (devinfo.ver == 7 && devinfo.is_baytrail) { + } else if (devinfo.platform == INTEL_PLATFORM_BYT) { mesa_logw("Bay Trail Vulkan support is incomplete"); } else if (devinfo.ver >= 8 && devinfo.ver <= 12) { /* Gfx8-12 fully supported */ @@ -851,7 +851,8 @@ anv_physical_device_try_create(struct anv_instance *instance, goto fail_base; } - if (device->info.ver >= 8 && !device->info.is_cherryview && + if (device->info.ver >= 8 && + device->info.platform != INTEL_PLATFORM_CHV && !anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN)) { result = vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED, "kernel missing softpin"); @@ -893,7 +894,7 @@ anv_physical_device_try_create(struct anv_instance *instance, goto fail_base; device->use_softpin = device->info.ver >= 8 && - !device->info.is_cherryview; + device->info.platform != INTEL_PLATFORM_CHV; assert(device->use_softpin == device->supports_48bit_addresses); device->has_context_isolation = @@ -1279,7 +1280,7 @@ void anv_GetPhysicalDeviceFeatures( .multiViewport = true, .samplerAnisotropy = true, .textureCompressionETC2 = pdevice->info.ver >= 8 || - pdevice->info.is_baytrail, + pdevice->info.platform == INTEL_PLATFORM_BYT, .textureCompressionASTC_LDR = has_astc_ldr, .textureCompressionBC = true, .occlusionQueryPrecise = true, @@ -2770,7 +2771,7 @@ anv_state_pool_emit_data(struct anv_state_pool *pool, size_t size, size_t align, static void anv_device_init_border_colors(struct anv_device *device) { - if (device->info.is_haswell) { + if (device->info.platform == INTEL_PLATFORM_HSW) { static const struct hsw_border_color border_colors[] = { [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = { .float32 = { 0.0, 0.0, 0.0, 0.0 } }, [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = { .float32 = { 0.0, 0.0, 0.0, 1.0 } }, diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 8f51f08e3d0..95c9e08fe82 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -5460,7 +5460,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, } #if GFX_VER == 9 - if (devinfo->is_geminilake) { + if (devinfo->platform == INTEL_PLATFORM_GLK) { /* Project: DevGLK * * "This chicken bit works around a hardware issue with barrier logic diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 81b07c40ade..765eaf4e8e6 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -2569,7 +2569,7 @@ genX(graphics_pipeline_create)( * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS * Stall" bit set. */ - if (!device->info.is_haswell && !device->info.is_baytrail) + if (device->info.platform == INTEL_PLATFORM_IVB) gfx7_emit_vs_workaround_flush(brw); #endif diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 9fb746654bb..075cccf9dee 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -514,7 +514,7 @@ VkResult genX(GetQueryPoolResults)( uint64_t result = slot[idx * 2 + 2] - slot[idx * 2 + 1]; /* WaDividePSInvocationCountBy4:HSW,BDW */ - if ((device->info.ver == 8 || device->info.is_haswell) && + if ((device->info.ver == 8 || device->info.verx10 == 75) && (1 << stat) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT) result >>= 2; @@ -1417,7 +1417,7 @@ void genX(CmdCopyQueryPoolResults)( /* WaDividePSInvocationCountBy4:HSW,BDW */ if ((cmd_buffer->device->info.ver == 8 || - cmd_buffer->device->info.is_haswell) && + cmd_buffer->device->info.verx10 == 75) && (1 << stat) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT) { result = mi_ushr32_imm(&b, result, 2); } diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 66964bf0b19..c43b6fe18cb 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -414,11 +414,11 @@ genX(emit_l3_config)(struct anv_batch *batch, * client (URB for all validated configurations) set to the * lower-bandwidth 2-bank address hashing mode. */ - const bool urb_low_bw = cfg->n[INTEL_L3P_SLM] && !devinfo->is_baytrail; + const bool urb_low_bw = cfg->n[INTEL_L3P_SLM] && devinfo->platform != INTEL_PLATFORM_BYT; assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]); /* Minimum number of ways that can be allocated to the URB. */ - const unsigned n0_urb = devinfo->is_baytrail ? 32 : 0; + const unsigned n0_urb = devinfo->platform == INTEL_PLATFORM_BYT ? 32 : 0; assert(cfg->n[INTEL_L3P_URB] >= n0_urb); anv_batch_write_reg(batch, GENX(L3SQCREG1), l3sqc) { @@ -430,7 +430,7 @@ genX(emit_l3_config)(struct anv_batch *batch, l3sqc.L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT; #else l3sqc.L3SQGeneralPriorityCreditInitialization = - devinfo->is_baytrail ? BYT_SQGPCI_DEFAULT : SQGPCI_DEFAULT; + devinfo->platform == INTEL_PLATFORM_BYT ? BYT_SQGPCI_DEFAULT : SQGPCI_DEFAULT; #endif l3sqc.L3SQHighPriorityCreditInitialization = SQHPCI_DEFAULT; } diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c index e2b33c3cc51..c5ec44b65af 100644 --- a/src/intel/vulkan/gfx8_cmd_buffer.c +++ b/src/intel/vulkan/gfx8_cmd_buffer.c @@ -441,7 +441,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) GENX(3DSTATE_SF_header), }; #if GFX_VER == 8 - if (cmd_buffer->device->info.is_cherryview) { + if (cmd_buffer->device->info.platform == INTEL_PLATFORM_CHV) { sf.CHVLineWidth = d->line_width; } else { sf.LineWidth = d->line_width; diff --git a/src/mesa/drivers/dri/i965/brw_batch.c b/src/mesa/drivers/dri/i965/brw_batch.c index 1d7da7abed3..9955018cda0 100644 --- a/src/mesa/drivers/dri/i965/brw_batch.c +++ b/src/mesa/drivers/dri/i965/brw_batch.c @@ -633,7 +633,7 @@ brw_finish_batch(struct brw_context *brw) !(brw->screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION)) gfx7_restore_default_l3_config(brw); - if (devinfo->is_haswell) { + if (devinfo->platform == INTEL_PLATFORM_HSW) { /* From the Haswell PRM, Volume 2b, Command Reference: Instructions, * 3DSTATE_CC_STATE_POINTERS > "Note": * diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 678ed1dcd6e..1b8ec47f585 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -78,7 +78,7 @@ brw_blorp_init(struct brw_context *brw) switch (devinfo->ver) { case 4: - if (devinfo->is_g4x) { + if (devinfo->verx10 == 45) { brw->blorp.exec = gfx45_blorp_exec; } else { brw->blorp.exec = gfx4_blorp_exec; @@ -91,7 +91,7 @@ brw_blorp_init(struct brw_context *brw) brw->blorp.exec = gfx6_blorp_exec; break; case 7: - if (devinfo->is_haswell) { + if (devinfo->verx10 == 75) { brw->blorp.exec = gfx75_blorp_exec; } else { brw->blorp.exec = gfx7_blorp_exec; diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index a4d49aaeca0..af8b3497060 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -670,7 +670,7 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.MaxPointSizeAA = 255.0; ctx->Const.PointSizeGranularity = 1.0; - if (devinfo->ver >= 5 || devinfo->is_g4x) + if (devinfo->verx10 >= 45) ctx->Const.MaxClipPlanes = 8; ctx->Const.GLSLFragCoordIsSysVal = true; diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index 2e23b347dcc..87e99ef26d3 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -331,7 +331,7 @@ emit: * * BRW_NEW_FRAGMENT_PROGRAM */ - if (devinfo->ver == 4 && !devinfo->is_g4x && + if (devinfo->verx10 == 40 && BITSET_TEST(fp->info.system_values_read, SYSTEM_VALUE_FRAG_COORD)) { BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index eb181f088a3..656159e79e7 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -254,7 +254,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, int size = glformat->Size; const struct intel_device_info *devinfo = &brw->screen->devinfo; const bool is_ivybridge_or_older = - devinfo->verx10 <= 70 && !devinfo->is_baytrail; + devinfo->verx10 < 70 || devinfo->platform == INTEL_PLATFORM_IVB; if (INTEL_DEBUG(DEBUG_VERTS)) fprintf(stderr, "type %s size %d normalized %d\n", diff --git a/src/mesa/drivers/dri/i965/brw_extensions.c b/src/mesa/drivers/dri/i965/brw_extensions.c index 8891b152c69..7f727991ceb 100644 --- a/src/mesa/drivers/dri/i965/brw_extensions.c +++ b/src/mesa/drivers/dri/i965/brw_extensions.c @@ -146,7 +146,8 @@ brw_init_extensions(struct gl_context *ctx) if (devinfo->ver >= 8) ctx->Const.GLSLVersion = 460; - else if (devinfo->is_haswell && can_do_pipelined_register_writes(brw->screen)) + else if (devinfo->platform == INTEL_PLATFORM_HSW && + can_do_pipelined_register_writes(brw->screen)) ctx->Const.GLSLVersion = 450; else if (devinfo->ver >= 7 && can_do_pipelined_register_writes(brw->screen)) ctx->Const.GLSLVersion = 420; @@ -165,7 +166,7 @@ brw_init_extensions(struct gl_context *ctx) ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130; ctx->Extensions.MESA_shader_integer_functions = ctx->Const.GLSLVersion >= 130; - if (devinfo->is_g4x || devinfo->ver >= 5) { + if (devinfo->verx10 >= 45) { ctx->Extensions.EXT_shader_framebuffer_fetch_non_coherent = true; ctx->Extensions.KHR_blend_equation_advanced = true; } @@ -294,7 +295,7 @@ brw_init_extensions(struct gl_context *ctx) ctx->Extensions.OES_viewport_array = true; } - if (devinfo->verx10 >= 75 || devinfo->is_baytrail) { + if (devinfo->verx10 >= 75 || devinfo->platform == INTEL_PLATFORM_BYT) { ctx->Extensions.ARB_robust_buffer_access_behavior = true; } @@ -302,7 +303,7 @@ brw_init_extensions(struct gl_context *ctx) ctx->Extensions.ARB_query_buffer_object = true; } - if (devinfo->ver >= 8 || devinfo->is_baytrail) { + if (devinfo->ver >= 8 || devinfo->platform == INTEL_PLATFORM_BYT) { /* For now, we can't enable OES_texture_view on Gen 7 because of * some piglit failures coming from * piglit/tests/spec/arb_texture_view/rendering-formats.c that need diff --git a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c index b44fd466f39..327340af88c 100644 --- a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c @@ -200,7 +200,7 @@ brw_lower_compressed_format(struct brw_context *brw, mesa_format format) /* No need to lower ETC formats on these platforms, * they are supported natively. */ - if (devinfo->ver >= 8 || devinfo->is_baytrail) + if (devinfo->ver >= 8 || devinfo->platform == INTEL_PLATFORM_BYT) return format; switch (format) { diff --git a/src/mesa/drivers/dri/i965/brw_mipmap_tree.h b/src/mesa/drivers/dri/i965/brw_mipmap_tree.h index c17e72e344a..956163bbff7 100644 --- a/src/mesa/drivers/dri/i965/brw_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/brw_mipmap_tree.h @@ -720,7 +720,7 @@ brw_miptree_needs_fake_etc(struct brw_context *brw, bool is_etc = _mesa_is_format_etc2(mt->format) || (mt->format == MESA_FORMAT_ETC1_RGB8); - return devinfo->ver < 8 && !devinfo->is_baytrail && is_etc; + return devinfo->ver < 8 && devinfo->platform != INTEL_PLATFORM_BYT && is_etc; } static inline bool diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 53eac1c178f..00aa82f991d 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -287,7 +287,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, } const struct intel_device_info *devinfo = &brw->screen->devinfo; - const unsigned len = (devinfo->is_g4x || devinfo->ver == 5) ? 6 : 5; + const unsigned len = (devinfo->verx10 == 45 || devinfo->ver == 5) ? 6 : 5; BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); @@ -307,7 +307,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, ((height + tile_y - 1) << 19)); OUT_BATCH(0); - if (devinfo->is_g4x || devinfo->ver >= 5) + if (devinfo->verx10 >= 45) OUT_BATCH(tile_x | (tile_y << 16)); else assert(tile_x == 0 && tile_y == 0); @@ -470,7 +470,7 @@ void brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) { const struct intel_device_info *devinfo = &brw->screen->devinfo; - const bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x; + const bool is_965 = devinfo->verx10 == 40; const uint32_t _3DSTATE_PIPELINE_SELECT = is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; @@ -585,7 +585,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) ADVANCE_BATCH(); } - if (devinfo->is_geminilake) { + if (devinfo->platform == INTEL_PLATFORM_GLK) { /* Project: DevGLK * * "This chicken bit works around a hardware issue with barrier logic @@ -698,7 +698,7 @@ void brw_upload_invariant_state(struct brw_context *brw) { const struct intel_device_info *devinfo = &brw->screen->devinfo; - const bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x; + const bool is_965 = devinfo->verx10 == 40; brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE); brw->last_pipeline = BRW_RENDER_PIPELINE; diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 0e9a25d6167..7c2cfdeb205 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -304,7 +304,7 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags) brw->workaround_bo, brw->workaround_bo_offset, 0); - if (devinfo->is_haswell) { + if (devinfo->platform == INTEL_PLATFORM_HSW) { /* Haswell needs addition work-arounds: * * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization": @@ -408,8 +408,8 @@ brw_init_pipe_control(struct brw_context *brw, break; case 7: brw->vtbl.emit_raw_pipe_control = - devinfo->is_haswell ? gfx75_emit_raw_pipe_control - : gfx7_emit_raw_pipe_control; + devinfo->verx10 == 75 ? + gfx75_emit_raw_pipe_control : gfx7_emit_raw_pipe_control; break; case 6: brw->vtbl.emit_raw_pipe_control = gfx6_emit_raw_pipe_control; @@ -419,8 +419,8 @@ brw_init_pipe_control(struct brw_context *brw, break; case 4: brw->vtbl.emit_raw_pipe_control = - devinfo->is_g4x ? gfx45_emit_raw_pipe_control - : gfx4_emit_raw_pipe_control; + devinfo->verx10 == 45 ? + gfx45_emit_raw_pipe_control : gfx4_emit_raw_pipe_control; break; default: unreachable("Unhandled Gen."); diff --git a/src/mesa/drivers/dri/i965/brw_screen.c b/src/mesa/drivers/dri/i965/brw_screen.c index 96c9ea617df..4d02e732c75 100644 --- a/src/mesa/drivers/dri/i965/brw_screen.c +++ b/src/mesa/drivers/dri/i965/brw_screen.c @@ -2071,7 +2071,7 @@ brw_detect_pipelined_so(struct brw_screen *screen) return false; /* See the big explanation about command parser versions below */ - if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2)) + if (screen->cmd_parser_version >= (devinfo->verx10 == 75 ? 7 : 2)) return true; /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the @@ -2388,14 +2388,14 @@ set_max_gl_versions(struct brw_screen *screen) dri_screen->max_gl_core_version = 33; if (can_do_pipelined_register_writes(screen)) { dri_screen->max_gl_core_version = 42; - if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen)) + if (screen->devinfo.platform == INTEL_PLATFORM_HSW && can_do_compute_dispatch(screen)) dri_screen->max_gl_core_version = 43; - if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen)) + if (screen->devinfo.platform == INTEL_PLATFORM_HSW && can_do_mi_math_and_lrr(screen)) dri_screen->max_gl_core_version = 45; } dri_screen->max_gl_compat_version = 30; dri_screen->max_gl_es1_version = 11; - dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30; + dri_screen->max_gl_es2_version = screen->devinfo.platform == INTEL_PLATFORM_HSW ? 31 : 30; break; case 6: dri_screen->max_gl_core_version = 33; @@ -2701,7 +2701,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen) /* Haswell requires command parser version 4 in order to have L3 * atomic scratch1 and chicken3 bits */ - if (devinfo->is_haswell && screen->cmd_parser_version >= 4) { + if (devinfo->verx10 == 75 && screen->cmd_parser_version >= 4) { screen->kernel_features |= KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3; } @@ -2711,7 +2711,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen) * MI_LOAD_REGISTER_REG (which all users of MI_MATH use). */ if (devinfo->ver >= 8 || - (devinfo->is_haswell && screen->cmd_parser_version >= 7)) { + (devinfo->verx10 == 75 && screen->cmd_parser_version >= 7)) { screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR; } diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index ca0118ed217..7a6a8cd64a5 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -317,7 +317,7 @@ void brw_init_state( struct brw_context *brw ) gfx9_init_atoms(brw); else if (devinfo->ver >= 8) gfx8_init_atoms(brw); - else if (devinfo->is_haswell) + else if (devinfo->verx10 >= 75) gfx75_init_atoms(brw); else if (devinfo->ver >= 7) gfx7_init_atoms(brw); @@ -325,7 +325,7 @@ void brw_init_state( struct brw_context *brw ) gfx6_init_atoms(brw); else if (devinfo->ver >= 5) gfx5_init_atoms(brw); - else if (devinfo->is_g4x) + else if (devinfo->verx10 >= 45) gfx45_init_atoms(brw); else gfx4_init_atoms(brw); diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index 81175467321..7f9b4cc6b8e 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -157,7 +157,7 @@ brw_calculate_urb_fence(struct brw_context *brw, unsigned csize, brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries; } - } else if (devinfo->is_g4x) { + } else if (devinfo->verx10 == 45) { brw->urb.nr_vs_entries = 64; if (check_urb_layout(brw)) { goto done; diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 36dbad1a1ba..5b430933e03 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -256,7 +256,8 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, * leaving normal texture swizzling to SCS. */ unsigned src_swizzle = - devinfo->is_haswell ? t->Attrib._Swizzle : key->swizzles[s]; + devinfo->platform == INTEL_PLATFORM_HSW ? + t->Attrib._Swizzle : key->swizzles[s]; for (int i = 0; i < 4; i++) { unsigned src_comp = GET_SWZ(src_swizzle, i); if (src_comp == SWIZZLE_ONE || src_comp == SWIZZLE_W) { @@ -271,7 +272,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, * request blue. Haswell can use SCS for this, but Ivybridge * needs a shader workaround. */ - if (!devinfo->is_haswell) + if (devinfo->platform != INTEL_PLATFORM_HSW) key->gather_channel_quirk_mask |= 1 << s; break; } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 940857425bf..08e90094a9f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -513,7 +513,7 @@ static void brw_update_texture_surface(struct gl_context *ctx, format == ISL_FORMAT_R32G32_SINT || format == ISL_FORMAT_R32G32_UINT)) { format = ISL_FORMAT_R32G32_FLOAT_LD; - need_green_to_blue = devinfo->is_haswell; + need_green_to_blue = devinfo->platform == INTEL_PLATFORM_HSW; } else if (devinfo->ver == 6) { /* Sandybridge's gather4 message is broken for integer formats. * To work around this, we pretend the surface is UNORM for diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 5f2464d114c..3db621bb46d 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -737,7 +737,7 @@ genX(emit_vertices)(struct brw_context *brw) * vertex element may poke over the end of the buffer by 2 bytes. */ const unsigned padding = - (GFX_VERx10 < 75 && !devinfo->is_baytrail) * 2; + (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT) * 2; const unsigned end = buffer->offset + buffer->size + padding; dw = genX(emit_vertex_buffer_state)(brw, dw, i, buffer->bo, buffer->offset, @@ -1795,7 +1795,7 @@ genX(upload_sf)(struct brw_context *brw) #if GFX_VER == 8 const struct intel_device_info *devinfo = &brw->screen->devinfo; - if (devinfo->is_cherryview) + if (devinfo->platform == INTEL_PLATFORM_CHV) sf.CHVLineWidth = brw_get_line_width(brw); else sf.LineWidth = brw_get_line_width(brw); @@ -2312,7 +2312,7 @@ genX(upload_vs_state)(struct brw_context *brw) } #endif - if (GFX_VER == 7 && devinfo->is_ivybridge) + if (GFX_VER == 7 && devinfo->platform == INTEL_PLATFORM_IVB) gfx7_emit_vs_workaround_flush(brw); #if GFX_VER >= 6 @@ -3249,7 +3249,9 @@ genX(upload_push_constant_packets)(struct brw_context *brw) &brw->wm.base, }; - if (GFX_VERx10 == 70 && !devinfo->is_baytrail && + + if (GFX_VERx10 == 70 && + devinfo->platform == INTEL_PLATFORM_IVB && stage_states[MESA_SHADER_VERTEX]->push_constants_dirty) gfx7_emit_vs_workaround_flush(brw); diff --git a/src/mesa/drivers/dri/i965/gfx6_queryobj.c b/src/mesa/drivers/dri/i965/gfx6_queryobj.c index d6067d3c08e..85db77f9035 100644 --- a/src/mesa/drivers/dri/i965/gfx6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gfx6_queryobj.c @@ -296,7 +296,7 @@ gfx6_queryobj_get_results(struct gl_context *ctx, * and correctly emitted the number of pixel shader invocations, but, * whomever forgot to undo the multiply by 4. */ - if (devinfo->ver == 8 || devinfo->is_haswell) + if (devinfo->ver == 8 || devinfo->verx10 == 75) query->Base.Result /= 4; break; diff --git a/src/mesa/drivers/dri/i965/gfx7_l3_state.c b/src/mesa/drivers/dri/i965/gfx7_l3_state.c index f7ef5c1d3e1..c088dc67247 100644 --- a/src/mesa/drivers/dri/i965/gfx7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gfx7_l3_state.c @@ -136,11 +136,11 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg) * client (URB for all validated configurations) set to the * lower-bandwidth 2-bank address hashing mode. */ - const bool urb_low_bw = has_slm && !devinfo->is_baytrail; + const bool urb_low_bw = has_slm && devinfo->platform != INTEL_PLATFORM_BYT; assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]); /* Minimum number of ways that can be allocated to the URB. */ - const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0); + const unsigned n0_urb = (devinfo->platform == INTEL_PLATFORM_BYT ? 32 : 0); assert(cfg->n[INTEL_L3P_URB] >= n0_urb); BEGIN_BATCH(7); @@ -148,8 +148,8 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg) /* Demote any clients with no ways assigned to LLC. */ OUT_BATCH(GFX7_L3SQCREG1); - OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : - devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT : + OUT_BATCH((devinfo->platform == INTEL_PLATFORM_HSW ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : + devinfo->platform == INTEL_PLATFORM_BYT ? VLV_L3SQCREG1_SQGHPCI_DEFAULT : IVB_L3SQCREG1_SQGHPCI_DEFAULT) | (has_dc ? 0 : GFX7_L3SQCREG1_CONV_DC_UC) | (has_is ? 0 : GFX7_L3SQCREG1_CONV_IS_UC) | diff --git a/src/mesa/drivers/dri/i965/gfx7_urb.c b/src/mesa/drivers/dri/i965/gfx7_urb.c index 79c28c15658..ff001084476 100644 --- a/src/mesa/drivers/dri/i965/gfx7_urb.c +++ b/src/mesa/drivers/dri/i965/gfx7_urb.c @@ -138,9 +138,9 @@ gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, * We've also seen some intermittent failures from SKL GT4 and BXT in * the past. */ - if (!devinfo->is_skylake && - !devinfo->is_broxton && - !devinfo->is_geminilake) + if (devinfo->platform != INTEL_PLATFORM_SKL && + devinfo->platform != INTEL_PLATFORM_BXT && + devinfo->platform != INTEL_PLATFORM_GLK) return; } @@ -172,7 +172,7 @@ gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, * * No such restriction exists for Haswell or Baytrail. */ - if (devinfo->verx10 <= 70 && !devinfo->is_baytrail) + if (devinfo->verx10 <= 70 && devinfo->platform != INTEL_PLATFORM_BYT) gfx7_emit_cs_stall_flush(brw); } @@ -251,7 +251,7 @@ gfx7_upload_urb(struct brw_context *brw, unsigned vs_size, tess_present, gs_present, entry_size, entries, start, NULL, &constrained); - if (devinfo->verx10 == 70 && !devinfo->is_baytrail) + if (devinfo->platform == INTEL_PLATFORM_IVB) gfx7_emit_vs_workaround_flush(brw); BEGIN_BATCH(8); diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c index e459c7db8b9..da195c87263 100644 --- a/src/mesa/drivers/dri/i965/hsw_queryobj.c +++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c @@ -337,7 +337,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query, * and correctly emitted the number of pixel shader invocations, but, * whomever forgot to undo the multiply by 4. */ - if (devinfo->ver == 8 || devinfo->is_haswell) + if (devinfo->ver == 8 || devinfo->platform == INTEL_PLATFORM_HSW) shr_gpr0_by_2_bits(brw); break; case GL_TIME_ELAPSED: diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c b/src/mesa/drivers/dri/i965/hsw_sol.c index 5c8fc7fa198..8d801e51ce9 100644 --- a/src/mesa/drivers/dri/i965/hsw_sol.c +++ b/src/mesa/drivers/dri/i965/hsw_sol.c @@ -199,7 +199,7 @@ hsw_pause_transform_feedback(struct gl_context *ctx, (struct brw_transform_feedback_object *) obj; const struct intel_device_info *devinfo = &brw->screen->devinfo; - if (devinfo->is_haswell) { + if (devinfo->platform == INTEL_PLATFORM_HSW) { /* Flush any drawing so that the counters have the right values. */ brw_emit_mi_flush(brw); @@ -229,7 +229,7 @@ hsw_resume_transform_feedback(struct gl_context *ctx, (struct brw_transform_feedback_object *) obj; const struct intel_device_info *devinfo = &brw->screen->devinfo; - if (devinfo->is_haswell) { + if (devinfo->platform == INTEL_PLATFORM_HSW) { /* Reload the SOL buffer offset registers. */ for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) { BEGIN_BATCH(3);