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r600g: compute tiling info in the pipe, not in the winsys 

The winsys doesn't need it.
This commit is contained in:
Marek Olšák 2011-09-11 14:53:07 +02:00
parent a94e33a8ef
commit 3603d15788
6 changed files with 133 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/gallium/drivers/r600/r600.h
View File

@ -84,7 +84,6 @@ struct r600_tiling_info {
enum radeon_family r600_get_family(struct radeon *rw);
enum chip_class r600_get_family_class(struct radeon *radeon);
struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
unsigned r600_get_minor_version(struct radeon *radeon);
unsigned r600_get_num_backends(struct radeon *radeon);

123
src/gallium/drivers/r600/r600_pipe.c
View File

@ -589,18 +589,140 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen,
return TRUE;
}
static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
{
switch ((tiling_config & 0xe) >> 1) {
case 0:
rscreen->tiling_info.num_channels = 1;
break;
case 1:
rscreen->tiling_info.num_channels = 2;
break;
case 2:
rscreen->tiling_info.num_channels = 4;
break;
case 3:
rscreen->tiling_info.num_channels = 8;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0x30) >> 4) {
case 0:
rscreen->tiling_info.num_banks = 4;
break;
case 1:
rscreen->tiling_info.num_banks = 8;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0xc0) >> 6) {
case 0:
rscreen->tiling_info.group_bytes = 256;
break;
case 1:
rscreen->tiling_info.group_bytes = 512;
break;
default:
return -EINVAL;
}
return 0;
}
static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
{
switch (tiling_config & 0xf) {
case 0:
rscreen->tiling_info.num_channels = 1;
break;
case 1:
rscreen->tiling_info.num_channels = 2;
break;
case 2:
rscreen->tiling_info.num_channels = 4;
break;
case 3:
rscreen->tiling_info.num_channels = 8;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0xf0) >> 4) {
case 0:
rscreen->tiling_info.num_banks = 4;
break;
case 1:
rscreen->tiling_info.num_banks = 8;
break;
case 2:
rscreen->tiling_info.num_banks = 16;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0xf00) >> 8) {
case 0:
rscreen->tiling_info.group_bytes = 256;
break;
case 1:
rscreen->tiling_info.group_bytes = 512;
break;
default:
return -EINVAL;
}
return 0;
}
static int r600_init_tiling(struct r600_screen *rscreen)
{
uint32_t tiling_config = rscreen->info.r600_tiling_config;
/* set default group bytes, overridden by tiling info ioctl */
if (r600_get_family_class(rscreen->radeon) <= R700) {
rscreen->tiling_info.group_bytes = 256;
} else {
rscreen->tiling_info.group_bytes = 512;
}
if (!tiling_config)
return 0;
if (r600_get_family_class(rscreen->radeon) <= R700) {
return r600_interpret_tiling(rscreen, tiling_config);
} else {
return evergreen_interpret_tiling(rscreen, tiling_config);
}
}
struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
{
struct r600_screen *rscreen;
struct radeon *radeon = radeon_create(ws);
if (!radeon) {
return NULL;
}
rscreen = CALLOC_STRUCT(r600_screen);
if (rscreen == NULL) {
radeon_destroy(radeon);
return NULL;
}
rscreen->ws = ws;
rscreen->radeon = radeon;
ws->query_info(ws, &rscreen->info);
if (r600_init_tiling(rscreen)) {
radeon_destroy(radeon);
FREE(rscreen);
return NULL;
}
rscreen->screen.winsys = (struct pipe_winsys*)ws;
rscreen->screen.destroy = r600_destroy_screen;
rscreen->screen.get_name = r600_get_name;
@ -621,7 +743,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
rscreen->screen.fence_finish = r600_fence_finish;
r600_init_screen_resource_functions(&rscreen->screen);
rscreen->tiling_info = r600_get_tiling_info(radeon);
util_format_s3tc_init();
util_slab_create(&rscreen->pool_buffers,

3
src/gallium/drivers/r600/r600_pipe.h
View File

@ -76,7 +76,8 @@ struct r600_screen {
struct pipe_screen screen;
struct radeon_winsys *ws;
struct radeon *radeon;
struct r600_tiling_info *tiling_info;
struct radeon_info info;
struct r600_tiling_info tiling_info;
struct util_slab_mempool pool_buffers;
unsigned num_contexts;

18
src/gallium/drivers/r600/r600_texture.c
View File

@ -93,19 +93,19 @@ static unsigned r600_get_block_alignment(struct pipe_screen *screen,
switch(array_mode) {
case V_038000_ARRAY_1D_TILED_THIN1:
p_align = MAX2(8,
((rscreen->tiling_info->group_bytes / 8 / pixsize)));
((rscreen->tiling_info.group_bytes / 8 / pixsize)));
break;
case V_038000_ARRAY_2D_TILED_THIN1:
p_align = MAX2(rscreen->tiling_info->num_banks,
(((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
rscreen->tiling_info->num_banks)) * 8;
p_align = MAX2(rscreen->tiling_info.num_banks,
(((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
rscreen->tiling_info.num_banks)) * 8;
break;
case V_038000_ARRAY_LINEAR_ALIGNED:
p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
break;
case V_038000_ARRAY_LINEAR_GENERAL:
default:
p_align = rscreen->tiling_info->group_bytes / pixsize;
p_align = rscreen->tiling_info.group_bytes / pixsize;
break;
}
return p_align;
@ -119,7 +119,7 @@ static unsigned r600_get_height_alignment(struct pipe_screen *screen,
switch (array_mode) {
case V_038000_ARRAY_2D_TILED_THIN1:
h_align = rscreen->tiling_info->num_channels * 8;
h_align = rscreen->tiling_info.num_channels * 8;
break;
case V_038000_ARRAY_1D_TILED_THIN1:
case V_038000_ARRAY_LINEAR_ALIGNED:
@ -145,14 +145,14 @@ static unsigned r600_get_base_alignment(struct pipe_screen *screen,
switch (array_mode) {
case V_038000_ARRAY_2D_TILED_THIN1:
b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
p_align * pixsize * h_align);
break;
case V_038000_ARRAY_1D_TILED_THIN1:
case V_038000_ARRAY_LINEAR_ALIGNED:
case V_038000_ARRAY_LINEAR_GENERAL:
default:
b_align = rscreen->tiling_info->group_bytes;
b_align = rscreen->tiling_info.group_bytes;
break;
}
return b_align;

120
src/gallium/winsys/r600/drm/r600_drm.c
View File

@ -41,11 +41,6 @@ enum chip_class r600_get_family_class(struct radeon *radeon)
return radeon->chip_class;
}
struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon)
{
return &radeon->tiling_info;
}
unsigned r600_get_clock_crystal_freq(struct radeon *radeon)
{
return radeon->info.r600_clock_crystal_freq;
@ -71,110 +66,6 @@ unsigned r600_get_minor_version(struct radeon *radeon)
return radeon->info.drm_minor;
}
static int r600_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
{
switch ((tiling_config & 0xe) >> 1) {
case 0:
radeon->tiling_info.num_channels = 1;
break;
case 1:
radeon->tiling_info.num_channels = 2;
break;
case 2:
radeon->tiling_info.num_channels = 4;
break;
case 3:
radeon->tiling_info.num_channels = 8;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0x30) >> 4) {
case 0:
radeon->tiling_info.num_banks = 4;
break;
case 1:
radeon->tiling_info.num_banks = 8;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0xc0) >> 6) {
case 0:
radeon->tiling_info.group_bytes = 256;
break;
case 1:
radeon->tiling_info.group_bytes = 512;
break;
default:
return -EINVAL;
}
return 0;
}
static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
{
switch (tiling_config & 0xf) {
case 0:
radeon->tiling_info.num_channels = 1;
break;
case 1:
radeon->tiling_info.num_channels = 2;
break;
case 2:
radeon->tiling_info.num_channels = 4;
break;
case 3:
radeon->tiling_info.num_channels = 8;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0xf0) >> 4) {
case 0:
radeon->tiling_info.num_banks = 4;
break;
case 1:
radeon->tiling_info.num_banks = 8;
break;
case 2:
radeon->tiling_info.num_banks = 16;
break;
default:
return -EINVAL;
}
switch ((tiling_config & 0xf00) >> 8) {
case 0:
radeon->tiling_info.group_bytes = 256;
break;
case 1:
radeon->tiling_info.group_bytes = 512;
break;
default:
return -EINVAL;
}
return 0;
}
static int radeon_drm_get_tiling(struct radeon *radeon)
{
uint32_t tiling_config = radeon->info.r600_tiling_config;
if (!tiling_config)
return 0;
if (radeon->chip_class == R600 || radeon->chip_class == R700) {
return r600_interpret_tiling(radeon, tiling_config);
} else {
return eg_interpret_tiling(radeon, tiling_config);
}
}
static unsigned radeon_family_from_device(unsigned device)
{
switch (device) {
@ -212,16 +103,12 @@ struct radeon *radeon_create(struct radeon_winsys *ws)
case CHIP_RS780:
case CHIP_RS880:
radeon->chip_class = R600;
/* set default group bytes, overridden by tiling info ioctl */
radeon->tiling_info.group_bytes = 256;
break;
case CHIP_RV770:
case CHIP_RV730:
case CHIP_RV710:
case CHIP_RV740:
radeon->chip_class = R700;
/* set default group bytes, overridden by tiling info ioctl */
radeon->tiling_info.group_bytes = 256;
break;
case CHIP_CEDAR:
case CHIP_REDWOOD:
@ -235,13 +122,9 @@ struct radeon *radeon_create(struct radeon_winsys *ws)
case CHIP_TURKS:
case CHIP_CAICOS:
radeon->chip_class = EVERGREEN;
/* set default group bytes, overridden by tiling info ioctl */
radeon->tiling_info.group_bytes = 512;
break;
case CHIP_CAYMAN:
radeon->chip_class = CAYMAN;
/* set default group bytes, overridden by tiling info ioctl */
radeon->tiling_info.group_bytes = 512;
break;
default:
fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
@ -249,9 +132,6 @@ struct radeon *radeon_create(struct radeon_winsys *ws)
break;
}
if (radeon_drm_get_tiling(radeon))
return NULL;
return radeon;
}

1
src/gallium/winsys/r600/drm/r600_priv.h
View File

@ -39,7 +39,6 @@ struct radeon {
struct radeon_info info;
unsigned family;
enum chip_class chip_class;
struct r600_tiling_info tiling_info;
};
/* these flags are used in register flags and added into block flags */