amd: update addrlib - trivial changes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17410>
This commit is contained in:
Marek Olšák
Marge Bot
parent
8179182660
commit
3514b73244
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@ -33,20 +33,20 @@
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#define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID))
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#define FAMILY_UNKNOWN 0x00
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#define FAMILY_TN 0x69
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#define FAMILY_SI 0x6E
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#define FAMILY_CI 0x78
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#define FAMILY_KV 0x7D
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#define FAMILY_VI 0x82
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#define FAMILY_POLARIS 0x82
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#define FAMILY_CZ 0x87
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#define FAMILY_AI 0x8D
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#define FAMILY_RV 0x8E
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#define FAMILY_NV 0x8F
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#define FAMILY_VGH 0x90
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#define FAMILY_TN 0x69 //# 105 / Trinity APUs
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#define FAMILY_SI 0x6E //# 110 / Southern Islands: Tahiti, Pitcairn, CapeVerde, Oland, Hainan
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#define FAMILY_CI 0x78 //# 120 / Sea Islands: Bonaire, Hawaii
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#define FAMILY_KV 0x7D //# 125 / Kaveri APUs: Spectre, Spooky, Kalindi, Godavari
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#define FAMILY_VI 0x82 //# 130 / Volcanic Islands: Iceland, Tonga, Fiji
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#define FAMILY_POLARIS 0x82 //# 130 / Polaris: 10, 11, 12
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#define FAMILY_CZ 0x87 //# 135 / Carrizo APUs: Carrizo, Stoney
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#define FAMILY_AI 0x8D //# 141 / Vega: 10, 20
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#define FAMILY_RV 0x8E //# 142 / Raven
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#define FAMILY_NV 0x8F //# 143 / Navi: 10
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#define FAMILY_VGH 0x90 //# 144 / Van Gogh
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#define FAMILY_GFX1100 0x91
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#define FAMILY_GFX1103 0x94
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#define FAMILY_RMB 0x92
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#define FAMILY_RMB 0x92 //# 146 / Rembrandt
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#define FAMILY_GC_10_3_6 0x95
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#define FAMILY_GC_10_3_7 0x97
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@ -62,69 +62,67 @@
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#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
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#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
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#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
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#define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB)
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#define FAMILY_IS_GFX1100(f) FAMILY_IS(f, GFX1100)
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#define FAMILY_IS_GFX1103(f) FAMILY_IS(f, GFX1103)
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#define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB)
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#define AMDGPU_UNKNOWN 0xFF
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#define AMDGPU_TAHITI_RANGE 0x05, 0x14
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#define AMDGPU_PITCAIRN_RANGE 0x15, 0x28
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#define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C
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#define AMDGPU_OLAND_RANGE 0x3C, 0x46
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#define AMDGPU_HAINAN_RANGE 0x46, 0xFF
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#define AMDGPU_TAHITI_RANGE 0x05, 0x14 //# 5 <= x < 20
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#define AMDGPU_PITCAIRN_RANGE 0x15, 0x28 //# 21 <= x < 40
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#define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C //# 41 <= x < 60
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#define AMDGPU_OLAND_RANGE 0x3C, 0x46 //# 60 <= x < 70
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#define AMDGPU_HAINAN_RANGE 0x46, 0xFF //# 70 <= x < max
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#define AMDGPU_BONAIRE_RANGE 0x14, 0x28
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#define AMDGPU_HAWAII_RANGE 0x28, 0x3C
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#define AMDGPU_BONAIRE_RANGE 0x14, 0x28 //# 20 <= x < 40
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#define AMDGPU_HAWAII_RANGE 0x28, 0x3C //# 40 <= x < 60
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#define AMDGPU_SPECTRE_RANGE 0x01, 0x41
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#define AMDGPU_SPOOKY_RANGE 0x41, 0x81
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#define AMDGPU_KALINDI_RANGE 0x81, 0xA1
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#define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF
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#define AMDGPU_SPECTRE_RANGE 0x01, 0x41 //# 1 <= x < 65
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#define AMDGPU_SPOOKY_RANGE 0x41, 0x81 //# 65 <= x < 129
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#define AMDGPU_KALINDI_RANGE 0x81, 0xA1 //# 129 <= x < 161
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#define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF //# 161 <= x < max
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#define AMDGPU_ICELAND_RANGE 0x01, 0x14
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#define AMDGPU_TONGA_RANGE 0x14, 0x28
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#define AMDGPU_FIJI_RANGE 0x3C, 0x50
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#define AMDGPU_ICELAND_RANGE 0x01, 0x14 //# 1 <= x < 20
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#define AMDGPU_TONGA_RANGE 0x14, 0x28 //# 20 <= x < 40
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#define AMDGPU_FIJI_RANGE 0x3C, 0x50 //# 60 <= x < 80
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#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A
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#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
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#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
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#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
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#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A //# 80 <= x < 90
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#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64 //# 90 <= x < 100
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#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E //# 100 <= x < 110
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#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF //# 110 <= x < max
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#define AMDGPU_CARRIZO_RANGE 0x01, 0x21
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#define AMDGPU_STONEY_RANGE 0x61, 0xFF
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#define AMDGPU_CARRIZO_RANGE 0x01, 0x21 //# 1 <= x < 33
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#define AMDGPU_BRISTOL_RANGE 0x10, 0x21 //# 16 <= x < 33
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#define AMDGPU_STONEY_RANGE 0x61, 0xFF //# 97 <= x < max
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#define AMDGPU_VEGA10_RANGE 0x01, 0x14
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#define AMDGPU_VEGA12_RANGE 0x14, 0x28
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#define AMDGPU_VEGA20_RANGE 0x28, 0x32
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#define AMDGPU_ARCTURUS_RANGE 0x32, 0x3C
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#define AMDGPU_ALDEBARAN_RANGE 0x3C, 0xFF
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#define AMDGPU_VEGA10_RANGE 0x01, 0x14 //# 1 <= x < 20
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#define AMDGPU_VEGA12_RANGE 0x14, 0x28 //# 20 <= x < 40
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#define AMDGPU_VEGA20_RANGE 0x28, 0xFF //# 40 <= x < max
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#define AMDGPU_RAVEN_RANGE 0x01, 0x81
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#define AMDGPU_RAVEN2_RANGE 0x81, 0x91
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#define AMDGPU_RENOIR_RANGE 0x91, 0xFF
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#define AMDGPU_RAVEN_RANGE 0x01, 0x81 //# 1 <= x < 129
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#define AMDGPU_RAVEN2_RANGE 0x81, 0x90 //# 129 <= x < 144
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#define AMDGPU_RENOIR_RANGE 0x91, 0xFF //# 145 <= x < max
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#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
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#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
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#define AMDGPU_NAVI14_RANGE 0x14, 0x28
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#define AMDGPU_NAVI21_RANGE 0x28, 0x32
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#define AMDGPU_NAVI22_RANGE 0x32, 0x3C
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#define AMDGPU_NAVI23_RANGE 0x3C, 0x46
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#define AMDGPU_NAVI24_RANGE 0x46, 0x50
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#define AMDGPU_NAVI10_RANGE 0x01, 0x0A //# 1 <= x < 10
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#define AMDGPU_NAVI12_RANGE 0x0A, 0x14 //# 10 <= x < 20
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#define AMDGPU_NAVI14_RANGE 0x14, 0x28 //# 20 <= x < 40
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#define AMDGPU_NAVI21_RANGE 0x28, 0x32 //# 40 <= x < 50
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#define AMDGPU_NAVI22_RANGE 0x32, 0x3C //# 50 <= x < 60
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#define AMDGPU_NAVI23_RANGE 0x3C, 0x46 //# 60 <= x < 70
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#define AMDGPU_NAVI24_RANGE 0x46, 0x50 //# 70 <= x < 80
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#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF
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#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF //# 1 <= x < max
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#define AMDGPU_GFX1100_RANGE 0x01, 0x10
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#define AMDGPU_GFX1101_RANGE 0x20, 0xFF
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#define AMDGPU_GFX1102_RANGE 0x10, 0x20
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#define AMDGPU_GFX1100_RANGE 0x01, 0x10 //# 01 <= x < 16
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#define AMDGPU_GFX1101_RANGE 0x20, 0xFF //# 32 <= x < 255
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#define AMDGPU_GFX1102_RANGE 0x10, 0x20 //# 16 <= x < 32
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#define AMDGPU_GFX1103_RANGE 0x01, 0xFF
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#define AMDGPU_GFX1103_RANGE 0x01, 0xFF //# 1 <= x < max
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#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF
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#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF //# 01 <= x < 255
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#define AMDGPU_GFX1036_RANGE 0x01, 0xFF
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#define AMDGPU_GFX1036_RANGE 0x01, 0xFF //# 1 <= x < max
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#define AMDGPU_GFX1037_RANGE 0x01, 0xFF
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#define AMDGPU_GFX1037_RANGE 0x01, 0xFF //# 1 <= x < max
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#define AMDGPU_EXPAND_FIX(x) x
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#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
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@ -157,6 +155,7 @@
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#define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
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#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
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#define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
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#define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
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#define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
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@ -164,8 +163,6 @@
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#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
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#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
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#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
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#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
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#define ASICREV_IS_ALDEBARAN(r) ASICREV_IS(r, ALDEBARAN)
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#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
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#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
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@ -2065,7 +2065,7 @@ BOOL_32 Lib::IsBlockTypeAvaiable(
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* Lib::BlockTypeWithinMemoryBudget
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*
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* @brief
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* Determine whether a new block type is acceptible based on memory waste ratio
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* Determine whether a new block type is acceptable based on memory waste ratio. Will favor larger block types.
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*
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* @return
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* N/A
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@ -148,6 +148,8 @@ union ADDR_BIT_SETTING
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* @brief Swizzle pattern information
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************************************************************************************************************************
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*/
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// Accessed by index representing the logbase2 of (8bpp/16bpp/32bpp/64bpp/128bpp)
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// contains the indices which map to 2D arrays SW_PATTERN_NIBBLE[0-9] which contain sections of an index equation. They are dependant on pipe# and bpe #
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struct ADDR_SW_PATINFO
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{
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UINT_8 maxItemCount;
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@ -3738,6 +3738,7 @@ const ADDR_SW_PATINFO GFX10_SW_VAR_Z_X_8xaa_RBPLUS_PATINFO[] =
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{ 3, 27, 344, 365, 124, } , // 64 pipes (32 PKRs) 16 bpe @ SW_VAR_Z_X 8xaa @ RbPlus
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};
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// Nibble 2D arrays contain arrays of sections of the index equation. An index equation depends on the swizzle mode, pipe#, and bpe#
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const UINT_64 GFX10_SW_PATTERN_NIBBLE01[][8] =
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{
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{X0, X1, X2, X3, Y0, Y1, Y2, Y3, }, // 0
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@ -4294,6 +4295,8 @@ const UINT_64 GFX10_SW_PATTERN_NIBBLE2[][4] =
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{Y4^X9^Y9, X4^Y4, Y2^Y5^X8, Z2^X5^Y8, }, // 507
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{Z3^Y4^X9^Y9, X4^Y4, Y1^Y5^X8, Z2^X5^Y8, }, // 508
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{Z3^Y4^X9^Y9, Y1^X4^Y4, X1^Y5^X8, Z2^X5^Y8, }, // 509
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{Y3^X5^Y5, Z0^X4^Y4, Y2, X3, }, // 510
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{Y3^X5^Y5, X2^X4^Y4, Y2, X3, }, // 511
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};
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const UINT_64 GFX10_SW_PATTERN_NIBBLE3[][4] =
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@ -93,7 +93,7 @@ const SwizzleModeFlags Gfx10Lib::SwizzleModeTable[ADDR_SW_MAX_TYPE] =
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{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
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{{0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_4KB_S_X
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{{0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0}}, // ADDR_SW_4KB_D_X
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{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
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{{0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0}}, // ADDR_SW_4KB_R_X
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{{0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_Z_X
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{{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_S_X
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@ -1460,12 +1460,12 @@ VOID Gfx10Lib::ConvertSwizzlePatternToEquation(
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ADDR_EQUATION* pEquation) ///< [out] equation converted from swizzle pattern
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const
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{
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// Get full swizzle pattern and store it as an ADDR_BIT_SETTING list
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ADDR_BIT_SETTING fullSwizzlePattern[20];
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GetSwizzlePatternFromPatternInfo(pPatInfo, fullSwizzlePattern);
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const ADDR_BIT_SETTING* pSwizzle = fullSwizzlePattern;
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const UINT_32 blockSizeLog2 = GetBlockSizeLog2(swMode);
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pEquation->numBits = blockSizeLog2;
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pEquation->stackedDepthSlices = FALSE;
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@ -1994,37 +1994,46 @@ VOID Gfx10Lib::InitEquationTable()
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{
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memset(m_equationTable, 0, sizeof(m_equationTable));
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// Iterate through resourceTypes, up to MaxRsrcType where a "resourceType" refers to AddrResourceType (1D/2D/3D)
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// resources. This starts with rsrcTypeIdx = 0, however there is an offset added that will start us off at
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// computing 2D resources.
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for (UINT_32 rsrcTypeIdx = 0; rsrcTypeIdx < MaxRsrcType; rsrcTypeIdx++)
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{
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// Add offset. Start iterating from ADDR_RSRC_TEX_2D
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const AddrResourceType rsrcType = static_cast<AddrResourceType>(rsrcTypeIdx + ADDR_RSRC_TEX_2D);
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// Iterate through the maximum number of swizzlemodes a type can hold
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for (UINT_32 swModeIdx = 0; swModeIdx < MaxSwModeType; swModeIdx++)
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{
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const AddrSwizzleMode swMode = static_cast<AddrSwizzleMode>(swModeIdx);
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// Iterate through the different bits-per-pixel settings (8bpp/16bpp/32bpp/64bpp/128bpp)
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for (UINT_32 elemLog2 = 0; elemLog2 < MaxElementBytesLog2; elemLog2++)
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{
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UINT_32 equationIndex = ADDR_INVALID_EQUATION_INDEX;
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// May or may not return a ADDR_SW_PATINFO for a completely different swizzle mode, essentially
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// overwriting the choice.
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const ADDR_SW_PATINFO* pPatInfo = GetSwizzlePatternInfo(swMode, rsrcType, elemLog2, 1);
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if (pPatInfo != NULL)
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{
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ADDR_ASSERT(IsValidSwMode(swMode));
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if (pPatInfo->maxItemCount <= 3)
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if (pPatInfo->maxItemCount <= 3) // Get a valid equationIndex
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{
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ADDR_EQUATION equation = {};
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// Passing in pPatInfo to get the addr equation
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ConvertSwizzlePatternToEquation(elemLog2, rsrcType, swMode, pPatInfo, &equation);
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equationIndex = m_numEquations;
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ADDR_ASSERT(equationIndex < EquationTableSize);
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// Updates m_equationTable[m_numEquations] to be the addr equation for this PatInfo
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m_equationTable[equationIndex] = equation;
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// Increment m_numEquations
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m_numEquations++;
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}
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else
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else // There is no equationIndex
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{
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// We only see "ill" equation from 64/128 BPE + 3D resource + SW_64KB_D_X under RB+ case
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ADDR_ASSERT((elemLog2 == 3) || (elemLog2 == 4));
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@ -2033,7 +2042,8 @@ VOID Gfx10Lib::InitEquationTable()
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ADDR_ASSERT(m_settings.supportRbPlus == 1);
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}
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}
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// equationIndex, which is used to look up equations in m_equationTable, will be cached for every
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// iteration in this nested for-loop
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m_equationLookupTable[rsrcTypeIdx][swModeIdx][elemLog2] = equationIndex;
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}
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}
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@ -2756,7 +2766,7 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeSurfaceInfoSanityCheck(
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* Gfx10Lib::HwlGetPreferredSurfaceSetting
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*
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* @brief
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* Internal function to get suggested surface information for cliet to use
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* Internal function to get suggested surface information for client to use
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*
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* @return
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* ADDR_E_RETURNCODE
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@ -3008,6 +3018,7 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlGetPreferredSurfaceSetting(
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allowedSwModeSet.value &= GetValidDisplaySwizzleModes(bpp);
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}
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if (allowedSwModeSet.value != 0)
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{
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#if DEBUG
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@ -3077,11 +3088,13 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlGetPreferredSurfaceSetting(
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allowedSwModeSet.swLinear = 0;
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}
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// A bitfield where each bit represents a block type. Each swizzle mode maps to a block.
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ADDR2_BLOCK_SET allowedBlockSet = GetAllowedBlockSet(allowedSwModeSet, pOut->resourceType);
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// Determine block size if there are 2 or more block type candidates
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if (IsPow2(allowedBlockSet.value) == FALSE)
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{
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// Tracks a valid SwizzleMode for each valid block type
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AddrSwizzleMode swMode[AddrBlockMaxTiledType] = {};
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swMode[AddrBlockLinear] = ADDR_SW_LINEAR;
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@ -3104,16 +3117,18 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlGetPreferredSurfaceSetting(
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swMode[AddrBlockThin64KB] = ADDR_SW_64KB_S;
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}
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// Tracks the size of each valid swizzle mode's surface in bytes
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UINT_64 padSize[AddrBlockMaxTiledType] = {};
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const UINT_32 ratioLow = computeMinSize ? 1 : (pIn->flags.opt4space ? 3 : 2);
|
||||
const UINT_32 ratioHi = computeMinSize ? 1 : (pIn->flags.opt4space ? 2 : 1);
|
||||
const UINT_64 sizeAlignInElement = Max(NextPow2(pIn->minSizeAlign) / (bpp >> 3), 1u);
|
||||
UINT_32 minSizeBlk = AddrBlockMicro;
|
||||
UINT_64 minSize = 0;
|
||||
UINT_32 minSizeBlk = AddrBlockMicro; // Tracks the most optimal block to use
|
||||
UINT_64 minSize = 0; // Tracks the minimum acceptable block type
|
||||
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT localOut = {};
|
||||
|
||||
// Iterate through all block types
|
||||
for (UINT_32 i = AddrBlockLinear; i < AddrBlockMaxTiledType; i++)
|
||||
{
|
||||
if (IsBlockTypeAvaiable(allowedBlockSet, static_cast<AddrBlockType>(i)))
|
||||
|
|
@ -3140,6 +3155,7 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlGetPreferredSurfaceSetting(
|
|||
}
|
||||
else
|
||||
{
|
||||
// Checks if the block type is within the memory budget but favors larger blocks
|
||||
if (BlockTypeWithinMemoryBudget(
|
||||
minSize,
|
||||
padSize[i],
|
||||
|
|
@ -4073,6 +4089,8 @@ const ADDR_SW_PATINFO* Gfx10Lib::GetSwizzlePatternInfo(
|
|||
UINT_32 numFrag ///< Number of fragment
|
||||
) const
|
||||
{
|
||||
// Now elemLog2 is going to be used to access the correct index insode of the pPatInfo array so we will start from
|
||||
// the right location
|
||||
const UINT_32 index = IsXor(swizzleMode) ? (m_colorBaseIndex + elemLog2) : elemLog2;
|
||||
const ADDR_SW_PATINFO* patInfo = NULL;
|
||||
const UINT_32 swizzleMask = 1 << swizzleMode;
|
||||
|
|
@ -4135,8 +4153,15 @@ const ADDR_SW_PATINFO* Gfx10Lib::GetSwizzlePatternInfo(
|
|||
{
|
||||
if (IsRtOptSwizzle(swizzleMode))
|
||||
{
|
||||
patInfo = m_settings.supportRbPlus ?
|
||||
GFX10_SW_64K_R_X_1xaa_RBPLUS_PATINFO : GFX10_SW_64K_R_X_1xaa_PATINFO;
|
||||
if (swizzleMode == ADDR_SW_4KB_R_X)
|
||||
{
|
||||
patInfo = NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
patInfo = m_settings.supportRbPlus ?
|
||||
GFX10_SW_64K_R_X_1xaa_RBPLUS_PATINFO : GFX10_SW_64K_R_X_1xaa_PATINFO;
|
||||
}
|
||||
}
|
||||
else if (IsZOrderSwizzle(swizzleMode))
|
||||
{
|
||||
|
|
@ -4230,6 +4255,10 @@ const ADDR_SW_PATINFO* Gfx10Lib::GetSwizzlePatternInfo(
|
|||
patInfo = m_settings.supportRbPlus ?
|
||||
GFX10_SW_4K_D_RBPLUS_PATINFO : GFX10_SW_4K_D_PATINFO;
|
||||
}
|
||||
else if (swizzleMode == ADDR_SW_4KB_R_X)
|
||||
{
|
||||
patInfo = NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
ADDR_ASSERT(swizzleMode == ADDR_SW_4KB_D_X);
|
||||
|
|
|
|||
|
|
@ -58,8 +58,8 @@ struct Gfx10ChipSettings
|
|||
UINT_32 supportRbPlus : 1;
|
||||
UINT_32 dsMipmapHtileFix : 1;
|
||||
UINT_32 dccUnsup3DSwDis : 1;
|
||||
UINT_32 : 2;
|
||||
UINT_32 reserved2 : 26;
|
||||
UINT_32 : 3;
|
||||
UINT_32 reserved2 : 25;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -80,10 +80,14 @@ const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR);
|
|||
const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
|
||||
(1u << ADDR_SW_256B_D);
|
||||
|
||||
|
||||
const UINT_32 Gfx10Blk4K_R_XMask = (1u << ADDR_SW_4KB_R_X);
|
||||
|
||||
const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) |
|
||||
(1u << ADDR_SW_4KB_D) |
|
||||
(1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_4KB_D_X);
|
||||
(1u << ADDR_SW_4KB_D_X) |
|
||||
(1u << ADDR_SW_4KB_R_X);
|
||||
|
||||
const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) |
|
||||
(1u << ADDR_SW_64KB_D) |
|
||||
|
|
@ -119,6 +123,7 @@ const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) |
|
|||
|
||||
const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_4KB_D_X) |
|
||||
(1u << ADDR_SW_4KB_R_X) |
|
||||
(1u << ADDR_SW_64KB_Z_X) |
|
||||
(1u << ADDR_SW_64KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_D_X) |
|
||||
|
|
@ -146,6 +151,7 @@ const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) |
|
|||
(1u << ADDR_SW_64KB_S) |
|
||||
(1u << ADDR_SW_64KB_S_T) |
|
||||
(1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_4KB_R_X) |
|
||||
(1u << ADDR_SW_64KB_Z_X) |
|
||||
(1u << ADDR_SW_64KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_D_X) |
|
||||
|
|
@ -167,8 +173,9 @@ const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10
|
|||
|
||||
const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask;
|
||||
|
||||
const UINT_32 Gfx10MsaaSwModeMask = Gfx10ZSwModeMask |
|
||||
Gfx10RenderSwModeMask;
|
||||
const UINT_32 Gfx10MsaaSwModeMask = (Gfx10ZSwModeMask |
|
||||
Gfx10RenderSwModeMask) &
|
||||
~Gfx10Blk4K_R_XMask;
|
||||
|
||||
const UINT_32 Dcn20NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
|
||||
(1u << ADDR_SW_4KB_S) |
|
||||
|
|
@ -397,6 +404,12 @@ private:
|
|||
UINT_32 log2Elem,
|
||||
UINT_32 numFrag) const;
|
||||
|
||||
/**
|
||||
* Will use the indices, "nibbles", to build an index equation inside pSwizzle
|
||||
*
|
||||
* @param pPatInfo Pointer to a patInfo. Contains indices mapping to the 2D nibble arrays which will be used to build an index equation.
|
||||
* @param pSwizzle Array to write the index equation to.
|
||||
*/
|
||||
VOID GetSwizzlePatternFromPatternInfo(
|
||||
const ADDR_SW_PATINFO* pPatInfo,
|
||||
ADDR_BIT_SETTING (&pSwizzle)[20]) const
|
||||
|
|
|
|||
|
|
@ -38,6 +38,12 @@
|
|||
#include <stdio.h>
|
||||
#include <ctype.h>
|
||||
|
||||
#define AMDGPU_ARCTURUS_RANGE 0x32, 0x3C
|
||||
#define AMDGPU_ALDEBARAN_RANGE 0x3C, 0xFF
|
||||
|
||||
#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
|
||||
#define ASICREV_IS_ALDEBARAN(r) ASICREV_IS(r, ALDEBARAN)
|
||||
|
||||
#ifdef _WIN32
|
||||
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
|
||||
#define DRM_CAP_SYNCOBJ 0x13
|
||||
|
|
|
|||
Loading…
Reference in New Issue