iris: Implement ARB_compute_variable_group_size
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
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GL_ARB_compute_variable_group_size on Iris.
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@ -96,6 +96,7 @@ iris_lost_context_state(struct iris_batch *batch)
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ice->state.dirty = ~0ull;
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ice->state.current_hash_scale = 0;
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memset(ice->state.last_block, 0, sizeof(ice->state.last_block));
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memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
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batch->last_surface_base_address = ~0ull;
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batch->last_aux_map_state = 0;
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@ -639,6 +639,9 @@ struct iris_context {
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bool window_space_position;
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/** The last compute group size */
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uint32_t last_block[3];
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/** The last compute grid size */
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uint32_t last_grid[3];
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/** Reference to the BO containing the compute grid size */
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@ -355,6 +355,12 @@ iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *grid)
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iris_update_compiled_compute_shader(ice);
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if (memcmp(ice->state.last_block, grid->block, sizeof(grid->block)) != 0) {
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memcpy(ice->state.last_block, grid->block, sizeof(grid->block));
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ice->state.dirty |= IRIS_DIRTY_CONSTANTS_CS;
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ice->state.shaders[MESA_SHADER_COMPUTE].sysvals_need_upload = true;
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}
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iris_update_grid_size_resource(ice, grid);
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iris_binder_reserve_compute(ice);
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@ -393,6 +393,7 @@ iris_setup_uniforms(const struct brw_compiler *compiler,
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unsigned patch_vert_idx = -1;
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unsigned ucp_idx[IRIS_MAX_CLIP_PLANES];
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unsigned img_idx[PIPE_MAX_SHADER_IMAGES];
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unsigned variable_group_size_idx = -1;
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memset(ucp_idx, -1, sizeof(ucp_idx));
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memset(img_idx, -1, sizeof(img_idx));
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@ -516,6 +517,21 @@ iris_setup_uniforms(const struct brw_compiler *compiler,
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nir_intrinsic_base(intrin) * 16));
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break;
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}
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case nir_intrinsic_load_local_group_size: {
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assert(nir->info.cs.local_size_variable);
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if (variable_group_size_idx == -1) {
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variable_group_size_idx = num_system_values;
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num_system_values += 3;
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for (int i = 0; i < 3; i++) {
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system_values[variable_group_size_idx + i] =
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BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X + i;
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}
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}
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b.cursor = nir_before_instr(instr);
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offset = nir_imm_int(&b, variable_group_size_idx * sizeof(uint32_t));
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break;
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}
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default:
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continue;
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}
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@ -1947,6 +1963,11 @@ iris_compile_cs(struct iris_context *ice,
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nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
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if (nir->info.cs.local_size_variable) {
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nir->info.cs.max_variable_local_size =
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iris_get_max_var_invocations(screen);
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}
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NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics);
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iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
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@ -443,6 +443,32 @@ iris_get_shader_param(struct pipe_screen *pscreen,
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}
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}
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static unsigned
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get_max_threads(const struct gen_device_info *devinfo)
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{
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/* Limit max_threads to 64 for the GPGPU_WALKER command. */
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return MIN2(64, devinfo->max_cs_threads);
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}
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uint32_t
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iris_get_max_var_invocations(const struct iris_screen *screen)
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{
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const unsigned max_threads = get_max_threads(&screen->devinfo);
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/* Constants used for ARB_compute_variable_group_size. The compiler will
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* use the maximum to decide which SIMDs can be used. If we top this like
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* max_invocations, that would prevent SIMD8 / SIMD16 to be considered.
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*
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* TODO: To avoid the trade off above between having the lower maximum
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* vs. always using SIMD32, keep all three shader variants (for each SIMD)
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* and select a suitable one at dispatch time.
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*/
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const uint32_t max_var_invocations =
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(max_threads >= 64 ? 8 : (max_threads >= 32 ? 16 : 32)) * max_threads;
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assert(max_var_invocations >= 512);
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return max_var_invocations;
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}
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static int
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iris_get_compute_param(struct pipe_screen *pscreen,
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enum pipe_shader_ir ir_type,
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@ -450,9 +476,8 @@ iris_get_compute_param(struct pipe_screen *pscreen,
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void *ret)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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const struct gen_device_info *devinfo = &screen->devinfo;
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const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
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const unsigned max_threads = get_max_threads(&screen->devinfo);
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const uint32_t max_invocations = 32 * max_threads;
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#define RET(x) do { \
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@ -494,13 +519,16 @@ iris_get_compute_param(struct pipe_screen *pscreen,
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case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
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RET((uint32_t []) { BRW_SUBGROUP_SIZE });
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case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
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/* MaxComputeVariableGroupInvocations */
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RET((uint64_t []) { iris_get_max_var_invocations(screen) });
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case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
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case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
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case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
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case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
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case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
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case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
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case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
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// XXX: I think these are for Clover...
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return 0;
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@ -227,4 +227,6 @@ iris_is_format_supported(struct pipe_screen *pscreen,
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void iris_disk_cache_init(struct iris_screen *screen);
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uint32_t iris_get_max_var_invocations(const struct iris_screen *screen);
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#endif
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@ -3214,6 +3214,10 @@ upload_sysvals(struct iris_context *ice,
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value = fui(ice->state.default_inner_level[0]);
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} else if (sysval == BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y) {
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value = fui(ice->state.default_inner_level[1]);
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} else if (sysval >= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X &&
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sysval <= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z) {
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unsigned i = sysval - BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X;
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value = ice->state.last_block[i];
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} else {
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assert(!"unhandled system value");
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}
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