svga: s/unsigned/VGPU10_OPCODE_TYPE/
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
This commit is contained in:
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a097a6f519
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338c35c427
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@ -1198,7 +1198,7 @@ emit_face_register(struct svga_shader_emitter_v10 *emit)
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*/
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static void
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emit_opcode(struct svga_shader_emitter_v10 *emit,
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unsigned vgpu10_opcode, boolean saturate)
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VGPU10_OPCODE_TYPE vgpu10_opcode, boolean saturate)
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{
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VGPU10OpcodeToken0 token0;
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@ -2053,7 +2053,7 @@ emit_decl_instruction(struct svga_shader_emitter_v10 *emit,
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*/
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static void
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emit_input_declaration(struct svga_shader_emitter_v10 *emit,
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unsigned opcodeType, unsigned operandType,
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VGPU10_OPCODE_TYPE opcodeType, unsigned operandType,
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unsigned dim, unsigned index, unsigned size,
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unsigned name, unsigned numComp,
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unsigned selMode, unsigned usageMask,
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@ -2411,7 +2411,7 @@ emit_input_declarations(struct svga_shader_emitter_v10 *emit)
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enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
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unsigned usage_mask = emit->info.input_usage_mask[i];
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unsigned index = emit->linkage.input_map[i];
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unsigned opcodeType, operandType;
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VGPU10_OPCODE_TYPE opcodeType, operandType;
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unsigned numComp, selMode;
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unsigned name;
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unsigned dim;
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@ -3106,7 +3106,7 @@ emit_resource_declarations(struct svga_shader_emitter_v10 *emit)
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static void
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emit_instruction_op1(struct svga_shader_emitter_v10 *emit,
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unsigned opcode,
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VGPU10_OPCODE_TYPE opcode,
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const struct tgsi_full_dst_register *dst,
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const struct tgsi_full_src_register *src,
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boolean saturate)
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@ -3120,7 +3120,7 @@ emit_instruction_op1(struct svga_shader_emitter_v10 *emit,
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static void
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emit_instruction_op2(struct svga_shader_emitter_v10 *emit,
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unsigned opcode,
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VGPU10_OPCODE_TYPE opcode,
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const struct tgsi_full_dst_register *dst,
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const struct tgsi_full_src_register *src1,
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const struct tgsi_full_src_register *src2,
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@ -3136,7 +3136,7 @@ emit_instruction_op2(struct svga_shader_emitter_v10 *emit,
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static void
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emit_instruction_op3(struct svga_shader_emitter_v10 *emit,
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unsigned opcode,
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VGPU10_OPCODE_TYPE opcode,
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const struct tgsi_full_dst_register *dst,
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const struct tgsi_full_src_register *src1,
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const struct tgsi_full_src_register *src2,
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@ -3484,7 +3484,7 @@ emit_arl_uarl(struct svga_shader_emitter_v10 *emit,
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{
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unsigned index = inst->Dst[0].Register.Index;
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struct tgsi_full_dst_register dst;
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unsigned opcode;
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VGPU10_OPCODE_TYPE opcode;
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assert(index < MAX_VGPU10_ADDR_REGS);
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dst = make_dst_temp_reg(emit->address_reg_index[index]);
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@ -5061,7 +5061,7 @@ emit_tex(struct svga_shader_emitter_v10 *emit,
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{
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const uint unit = inst->Src[1].Register.Index;
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const enum tgsi_texture_type target = inst->Texture.Texture;
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unsigned opcode;
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VGPU10_OPCODE_TYPE opcode;
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struct tgsi_full_src_register coord;
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int offsets[3];
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struct tex_swizzle_info swz_info;
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@ -5111,7 +5111,7 @@ emit_txp(struct svga_shader_emitter_v10 *emit,
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{
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const uint unit = inst->Src[1].Register.Index;
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const enum tgsi_texture_type target = inst->Texture.Texture;
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unsigned opcode;
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VGPU10_OPCODE_TYPE opcode;
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int offsets[3];
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unsigned tmp = get_temp_index(emit);
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struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
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@ -5263,7 +5263,8 @@ emit_txl_txb(struct svga_shader_emitter_v10 *emit,
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const struct tgsi_full_instruction *inst)
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{
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const enum tgsi_texture_type target = inst->Texture.Texture;
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unsigned opcode, unit;
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VGPU10_OPCODE_TYPE opcode;
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unsigned unit;
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int offsets[3];
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struct tgsi_full_src_register coord, lod_bias;
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struct tex_swizzle_info swz_info;
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