radeonsi: set VGT_LS_HS_CONFIG for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
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09d02fa463
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3344699243
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@ -174,6 +174,7 @@ void si_begin_new_cs(struct si_context *ctx)
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ctx->last_gs_out_prim = -1;
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ctx->last_prim = -1;
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ctx->last_multi_vgt_param = -1;
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ctx->last_ls_hs_config = -1;
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ctx->last_rast_prim = -1;
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ctx->last_sc_line_stipple = ~0;
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ctx->emit_scratch_reloc = true;
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@ -48,7 +48,7 @@
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#define SI_MAX_DRAW_CS_DWORDS \
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(/*scratch:*/ 3 + /*derived prim state:*/ 3 + \
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/*draw regs:*/ 16 + /*draw packets:*/ 31 +\
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/*draw regs:*/ 18 + /*draw packets:*/ 31 +\
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/*derived tess state:*/ 19)
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/* Instruction cache. */
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@ -234,6 +234,7 @@ struct si_context {
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int last_gs_out_prim;
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int last_prim;
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int last_multi_vgt_param;
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int last_ls_hs_config;
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int last_rast_prim;
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unsigned last_sc_line_stipple;
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int current_rast_prim; /* primitive type after TES, GS */
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@ -321,6 +321,24 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
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}
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static unsigned si_get_ls_hs_config(struct si_context *sctx,
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const struct pipe_draw_info *info,
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unsigned num_patches)
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{
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unsigned num_output_cp;
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if (!sctx->tes_shader)
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return 0;
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num_output_cp = sctx->tcs_shader ?
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sctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
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info->vertices_per_patch;
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return S_028B58_NUM_PATCHES(num_patches) |
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S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
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S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
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}
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static void si_emit_scratch_reloc(struct si_context *sctx)
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{
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struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
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@ -374,27 +392,31 @@ static void si_emit_draw_registers(struct si_context *sctx,
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struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
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unsigned prim = si_conv_pipe_prim(info->mode);
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unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
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unsigned ia_multi_vgt_param, num_patches = 0;
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unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
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if (sctx->tes_shader)
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si_emit_derived_tess_state(sctx, info, &num_patches);
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ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
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ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
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/* Draw state. */
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if (prim != sctx->last_prim ||
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ia_multi_vgt_param != sctx->last_multi_vgt_param) {
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ia_multi_vgt_param != sctx->last_multi_vgt_param ||
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ls_hs_config != sctx->last_ls_hs_config) {
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if (sctx->b.chip_class >= CIK) {
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radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
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radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
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radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
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radeon_emit(cs, 0); /* VGT_LS_HS_CONFIG */
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radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
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} else {
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r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
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r600_write_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
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r600_write_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
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}
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sctx->last_prim = prim;
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sctx->last_multi_vgt_param = ia_multi_vgt_param;
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sctx->last_ls_hs_config = ls_hs_config;
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}
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if (gs_out_prim != sctx->last_gs_out_prim) {
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